Unable to boot up the i.MX8M Plus, even no UART message

[Jimmychea]

Hi, our custom board design are following the I.MX8M PLUS EVK design(Same LPDDR4 RAM), but our custom board unable to boot up and no error message output on UART(A53). May i know how to continue to debug to narrow down the issue ? (We are suspecting the LPDDR4 RAM issue.)

[Jimmychea]

But i can't see any output message via UART? After enable debugging message, i should see any output messages ?

[khang_letruong]

So that might not be the issue of LPDDR4 as you said. That could be inverted Tx, Rx because the BootROM could send some message out.

[khang_letruong]

Hi @Jimmychea ,

If you suspect the LPDDR4 issue, you can enable relevant debugging messages. Mine is for LF5.10.72: 

From e79f996f4fb168a52ebc67e00c8bb05fd02d7460 Mon Sep 17 00:00:00 2001
From: l4es <linux4es@gmail.com>
Date: Fri, 21 Jul 2023 11:09:49 +0700
Subject: [PATCH 2/3] drivers: ddr: Enable debugging for DDR memory

---
 drivers/ddr/imx/imx8m/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile
index bd9bcb8d53..dd68d40544 100644
--- a/drivers/ddr/imx/imx8m/Makefile
+++ b/drivers/ddr/imx/imx8m/Makefile
@@ -4,6 +4,8 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #

+KBUILD_CFLAGS += -D DEBUG=1
+
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o ddr_init.o
 endif
-- 
2.17.1

And relevant messages on the console would be :

U-Boot SPL 2021.04-lf_v2021.04+g35b1ab7774 (Sep 27 2022 - 02:05:23 +0000)
DDRINFO: start DRAM init
DDRINFO: cfg clk
DDRINFO: DRAM rate 3000MTS
DDRINFO: ddrc config start
DDRINFO: ddrc config done
DDRINFO:ddrphy config start
DRAM PHY training for 3000MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
[PMU Major message = 0x0000000d]
[PMU Major message = 0x00000000]
[PMU Major message = 0x00000002]
[PMU Major message = 0x00000001]
[PMU Major message = 0x0000000a]
[PMU Major message = 0x000000fd]
[PMU Major message = 0x000000fe]
[PMU Major message = 0x00000004]
[PMU Major message = 0x00000003]
[PMU Major message = 0x00000009]
[PMU Major message = 0x00000007]
Training PASS
DRAM PHY training for 400MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
[PMU Major message = 0x0000000d]
[PMU Major message = 0x00000000]
[PMU Major message = 0x00000002]
[PMU Major message = 0x00000001]
[PMU Major message = 0x000000fd]
[PMU Major message = 0x000000fe]
[PMU Major message = 0x00000004]
[PMU Major message = 0x00000003]
[PMU Major message = 0x00000009]
[PMU Major message = 0x00000007]
Training PASS
DRAM PHY training for 100MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
[PMU Major message = 0x0000000d]
[PMU Major message = 0x00000000]
[PMU Major message = 0x00000002]
[PMU Major message = 0x00000001]
[PMU Major message = 0x000000fd]
[PMU Major message = 0x000000fe]
[PMU Major message = 0x00000004]
[PMU Major message = 0x00000003]
[PMU Major message = 0x00000009]
[PMU Major message = 0x00000007]
Training PASS
DRAM PHY training for 3000MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
[PMU Major message = 0x00000000]
[PMU Major message = 0x00000006]
[PMU Major message = 0x00000006]
[PMU Major message = 0x00000005]
[PMU Major message = 0x00000005]
[PMU Major message = 0x00000007]
Training PASS
DDRINFO: ddrphy config done
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
SEC0:  RNG instantiated
Normal Boot
WDT:   Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
NOTICE:  BL31: v2.4(release):lf-5.10.72-2.2.3-0-g5f3ed37b8
NOTICE:  BL31: Built : 09:02:12, Oct 12 2022

[Jimmychea]

Can you provide the steps on how to add the debug messages into BSP and rebuild ?

[Jimmychea]

I able to enable the debug messages into Uboot. The below picture showing the DDR log messages, may i know what is the issue, and how to resolve it ? Thanks

[khang_letruong · Accepted solution]

Hi @Jimmychea ,

Obviously, it is NOT the problem of UART but the DDR training was NOT passed compared to the log I shared. You'd better ensure that the DDR stress testing had been passed as well before generating the lpddr4_timing.c file used in u-Boot.

Best Regards,

Khang

[Jimmychea]

ya, UART issue and LPDDR4 RAM issue have been resolved, but i encountered new issue, i will create a new post for it. Thanks.