Uboot Redirect to IRAM on MX6DL

[tony_l_cai]

Hi, all

       I want to redirect the uboot to IRAM. The uboot has cut the size so small that it can be put into IRAM completely(IRAM is 128k, and uboot.imx is 119k). But when I change the  CONFIG_SYS_TEXT_BASE to 0x90 0000(the IRAM base addr). the system cannot work(no log output). So how to modify to redirect? Thank you ~

[ranjithhebbar]

Hi all,

          I am working on i.MX6UL custom board. First I would like to know how to reduce the u-boot size i.e u-boot.imx from 350KB to around 64KB. We have currently iRAM size of 128KB in that available free area is 68KB. So anyone have better idea to reduce the size of u-boot.imx to 64KB and how to fit into SRAM. Need your input guys tony.l.cai‌ igorpadykov‌ BiyongSUN‌

Best Regards,

Ranjith Hebbar V S

[tony_l_cai]

Hi Sun,

My uboot was cut and downloaded in IRAM, I test DDR by it. And from my test,our DDR density is 1GB,and the CS0_END is 0x27,from FSL expression DDR_CS_SIZE/32MB +0x07=CS0_END,so I confirm the end addr is 0x5000 0000,ok,we can end at 0x4fff ffff,but when mtest 0x1000 0000 0x4fff ffff, the test always pours out the failure log:

FAILURE (read/write): @ 0x1001bd68: expected 0xf403d90a, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd6c: expected 0xf403d909, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd70: expected 0xf403d908, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd74: expected 0xf403d907, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd78: expected 0xf403d906, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd7c: expected 0xf403d905, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd80: expected 0xf403d904, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd84: expected 0xf403d903, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd88: expected 0xf403d902, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd8c: expected 0xf403d901, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd90: expected 0xf403d900, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd94: expected 0xf403d8ff, actual 0x00000000)

FAILURE (read/write): @ 0x1001bd98: expected 0xf403d8fe, actual 0x00000000)

And I found that mtest ,at the beginning, will stuck there for long time,just like hanging, then it will pour out the log. and I dont know whether the accuracy of the DDR W/R test  will be impacted after hanging.

[BiyongSUN]

Could you please disable the cache and try your mtest

I want to know about the DDR calibration result/ stress test for this board.

i.MX6/7 DDR Stress Test Tool V2.51

Have you "applied" the calibration result to the uboot DCD.

When you manually write to the address by DDR stress test, which is wrong for mtest, what is the result?

[tony_l_cai]

Hi Sun，

I received your ANDVANCED DDR Test tool JUST NOW, as I previous reply, cause your old version tool have some bugs that the ddr cannot run on Android 5.0 stably when the DDR DCD params have been passed by the old version DDR test tool. So I just downloaded the image into IRAM to test DDR and seek the valuable ways to test DDR. Though you have some ADVANCED DDR Test tool,I will try it and confirm whether the bugs are on this new version tool.

[BiyongSUN]

Please double check the DDR calibration results from DDR stress test tool are correctly applied to the uboot.

[tony_l_cai]

Hi, Sun

I have confirmed what you said for lot times before. And for avoiding this low fault, why do your tool not generate the uboot cfg directly? Its so easy for FSL.

[BiyongSUN]

In the 3.0.35 BSP relase, the DCD is in the flash_header.S. But in the new BSP 3.10.XX and 3.14.xx. It is in a  configuration file for uboot mkimage(located in uboot\tools). imximage.c works a one of its "plugin". We need to conside the modularization of a design. But I will pass your requirement.

Also you can post your suggestion to i.MX6/7 DDR Stress Test Tool V2.51

[tony_l_cai]

Hi Sun,

Yes,in your previous reply,you give me a method about this uboot standalone to test DDR. Actually, because of the IRAM limit,the image which was downloaded into the IRAM had cut the uboot standalone app,I didn't adopt this way to test DDR. But I also run mtest in IRAM, Do you mean that though I dont use the uboot standalone app, I still need to implement the "printf" in IRAM?

And though I download the whole uboot in IRAM, still have some code to be load in DDR? Is that so? I don't know, I just guess.

[BiyongSUN]

You don't now need to implement the printf if you don't use the uboot standalone.

But one thing you need to take care is you test the right configuration range of the DDR, which is mapping by CS0_END.

Also you need to apply the DDR parameters in DCD.

Note: the whole memory range is 3840MB.

[tony_l_cai]

Hi Sun，

Could we discuss that why cannot test the whole DDR when img downloads into IRAM?

[BiyongSUN]

You could test the whole DDR. But as I mentioned in previous replied if you use the uboot standalone app, when you test the DDR writing, it will destory the uboot code in DDR. That code such as printf is used by the uboot standalone app. That is why I said "suggest if you want to test the whole DDR, implement the "printf" inside the mtest.Cause the test will destroy the uboot itself, which has some stubs and function calling."

[tony_l_cai]

Thank you for your help~

Sorry, our DDR is DDR3,and  yes ,all params are generated by aid.

Our DDR(total 1GB) is combined by 4 pcs DDR3L(16bit),and is it the addr is from 0x1000 0000 to 0x3fff ffff?

[BiyongSUN]

Another thing you need to add is.

You need to add one more bank for DDR.

Now it is only one bank in ocram for uboot to know.

#define CONFIG_NR_DRAM_BANKS  1

#define PHYS_SDRAM   0x908000

#define PHYS_SDRAM_SIZE   SZ_128K

[tony_l_cai]

Hi sun,

What's the function of the CONFIG_NR_DRAM_BANKS,

and In our board, 4 pcs DDR3L combine to 1 channel 64bit DDR,and every piece DDR3L have 8banks, so the   CONFIG_NR_DRAM_BANKS=32 ?

[BiyongSUN]

The BANK definition is uboot is a software deifintion for a continuous memory range.

Normally in the i.MX6 has one bank for 1-channel DDR3 with the base address 0x10000000

and  two banks for 2-channel LPDDR2 with base 0x10000000 and 0x80000000

[BiyongSUN]

The address space depends on your hardware design as I mentioned in previous reply.

But you still can see it during the ddr stress test, or you can find it in the ddr stress test script.

[igorpadykov]

Hi Tony

seems CONFIG_SYS_TEXT_BASE is used by ROM as start address, refer to

attached  AN4581 Figure6, so since ROM also uses iRAM,  CONFIG_SYS_TEXT_BASE

should not be set at beginning, try for example with offset 0x00907000 or higher.

Best regards

igor

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[tony_l_cai]

Hi,igor

thank you for your help, I have cut the uboot to 97k,and I have tested it in ddr, it works ok, and then I redirected it from 0x908000, but no log, Could you help me?

[BiyongSUN]

what's the use case or purpose to fit the uboot inside the iram?

With the code size increasing in uboot, it is hard to do that in new uboot version.

If you can provide the use case, maybe we can figure out the alternative way for you.

[tony_l_cai]

Hi, Sun

I want to load the uboot in IRAM and use the cmd "mtest" to test the whole ddr. And Maybe you will recommand me to test ddr by imx ddr stress tool, Because we find this tool can not cover all the ddr test in our one project.(one case is on Android 5.0 MX6DL,and I have push the case to the FSL and FAE support,and still no reply,but we find the mtest can test the issue),so we want to implement this function. Could help me? Thank you~