USB3 superspeed errors, PTN36043 configuration

[thomasdoerfler]

We are currently deeply inspecting the i.MX8M USB3 superspeed interface, on our custom design and also on the i.MX8M EVK. With some combinations of cables and notebook, we experience communication errors.

Currently we suspect that the PTN36043 mux/redriver is not configured correctly, regarding the de-emphasis/equalization/tx level settings using the CHx_SETx pins. The i.MX8M EVK has the corresponding CHx_SETx pins tied to high by default, another answer in this forum implies that an "all open" setting would be the best starting point. BTW: the i.MX8M EVK and our custom design have rather short USB traces.

So: is there any experience from NXP or other designers regarding the CHx_SETx pin settings?

regards,

Thomas.

[reyes]

Hi,

There are no reports of communication errors using the PTN36043A super speed interface.

When PTN36043A is not being powered (i.e., VDD1V8 = 0 V), special steps should be done to prevent back-current issues on control pins such SEL or CH1/2_SET1/2 pins when these pins' states are not low. These pins can be controlled through two different ways. – pull-up/pull-down resistors - make sure these pull-up resistors' VDD is the same power source as to power PTN36043A. When power to PTN36043A is off, power to these pull-up resistors will be off as well. – external processor's GPIO - if PTN36043A is turned off when the external processor's power stays on, processor should configure these GPIOs connected to these control pins as output low (< 0.4 V) or tri-state mode (configure GPIOs as input mode). This will make sure no current will be flowing into PTN36043A through these control pins.

The recommended value of the external pull-up/pull-down resistor is 30 kohms.

Make sure you have configured the CHx_SETx according to your high-speed signal path:

Regards,

Jose