USB2/3 Compliance Testing in i.mx8QM

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

USB2/3 Compliance Testing in i.mx8QM

Jump to solution
975 Views
YukioOyama
Contributor III

Hi all,

We are developing a USB host device running Linux OS on iMX8QuadMax.

This device supports USB 2.0 High Speed and USB 3.0 SuperSpeed (it is a host device).

I want to test compliance tests to verify electrical characteristics. However, these tests require a test signal.

 

For USB2.0 Hi-speed

4 test modes are required for testing.

Does your Linux include EHSETT by default?  If so, how is it called and used?

If your Linux does not include it, do you know of any source code similar to EHSETT?

I don't care if it's code by an outside open communitiy, please let me know.

 

For USB3.0 Super Speed

Does your i.mx8qm automatically transition to compliance mode?

YukioOyama_0-1675316788149.png

If the transition were automatic, we would have nothing to do.

If it does not transition automatically, how do we generate CP0-7 signals? Please let me know the procedure.

 

Best Regards,

Yukio Oyama

0 Kudos
Reply
1 Solution
958 Views
joanxie
NXP TechSupport
NXP TechSupport

1) can use memtool

2) refer to the register as below

Adjust USB3.0 to compliance mode registers--PORTSC1USB3(offset: 1_0490h)

/unit_tests/memtool 0x5b130490=0x0a000340

Name

PORTSC1USB3

Description

USB3 Port Status and Control

Bit #

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Reset value

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Field definitions

WPR

DR

Reserved

Reserved

WOE

WOE

WOE

CAS

CEC

PLC

PRC

OCC

WRC

PEC

CSC

LWS

Bit #

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reset value

0

0

0

0

0

1

1

0

0

0

0

0

0

1

1

1

Field definitions

 

PIC

PortSpeed

PP

PLS

PR

OCA

Reserved

PED

CCS

Signal Names

Description

8-5

PLS

Port Link State (PLS), RWS. Default = RxDetect ('5'). This field is used to power manage the port and reflects its current link state. When the port is in the Enabled state, system software may set the link U state by writing this field. System software may also write this field to force a Disabled to Disconnected state transition of the port. Write Values: 0: The link shall transition to a U0 state from any of the U states. 3: The link shall transition to a U3 state from the U0 state. This action selectively suspends the device connected to this port. While the Port Link State = U3, the hub does not propagate downstream-directed traffic to this port, but the hub shall respond to resume signaling from the port. 5: If the port is in the Disabled state (PLS = Disabled, PP = '1'), then the link shall transition to a RxDetect state and the port shall transition to the Disconnected state, else ignored. 1-2,4,6-15: Ignored. State Encoding: 0: Link is in the U0 State, 1: Link is in the U1 State, 2: Link is in the U2 State, 3: Link is in the U3 State (Device Suspended), 4: Link is in the Disabled State, 5: Link is in the RxDetect State, 6: Link is in the Inactive State, 7: Link is in the Polling State, 8: Link is in the Recovery State, 9: Link is in the Hot Reset State, 10: Link is in the Compliance Mode State, 11: Link is in the Test Mode State, 12-14: Reserved, 15: Link is in the Resume State. Note: The Port Link State Write Strobe (LWS) shall also be set to '1' to write this field. This field is undefined if PP = '0'. Note: Transitions between different states are not reflected until the transition is complete. Refer to section 4.19 of xHCI specification for PLS transition conditions. Refer to sections 4.15.2 and 4.23.5 for more information on the use of this field

  • PORTSC1USB3 field descriptions

View solution in original post

0 Kudos
Reply
4 Replies
959 Views
joanxie
NXP TechSupport
NXP TechSupport

1) can use memtool

2) refer to the register as below

Adjust USB3.0 to compliance mode registers--PORTSC1USB3(offset: 1_0490h)

/unit_tests/memtool 0x5b130490=0x0a000340

Name

PORTSC1USB3

Description

USB3 Port Status and Control

Bit #

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Reset value

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Field definitions

WPR

DR

Reserved

Reserved

WOE

WOE

WOE

CAS

CEC

PLC

PRC

OCC

WRC

PEC

CSC

LWS

Bit #

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reset value

0

0

0

0

0

1

1

0

0

0

0

0

0

1

1

1

Field definitions

 

PIC

PortSpeed

PP

PLS

PR

OCA

Reserved

PED

CCS

Signal Names

Description

8-5

PLS

Port Link State (PLS), RWS. Default = RxDetect ('5'). This field is used to power manage the port and reflects its current link state. When the port is in the Enabled state, system software may set the link U state by writing this field. System software may also write this field to force a Disabled to Disconnected state transition of the port. Write Values: 0: The link shall transition to a U0 state from any of the U states. 3: The link shall transition to a U3 state from the U0 state. This action selectively suspends the device connected to this port. While the Port Link State = U3, the hub does not propagate downstream-directed traffic to this port, but the hub shall respond to resume signaling from the port. 5: If the port is in the Disabled state (PLS = Disabled, PP = '1'), then the link shall transition to a RxDetect state and the port shall transition to the Disconnected state, else ignored. 1-2,4,6-15: Ignored. State Encoding: 0: Link is in the U0 State, 1: Link is in the U1 State, 2: Link is in the U2 State, 3: Link is in the U3 State (Device Suspended), 4: Link is in the Disabled State, 5: Link is in the RxDetect State, 6: Link is in the Inactive State, 7: Link is in the Polling State, 8: Link is in the Recovery State, 9: Link is in the Hot Reset State, 10: Link is in the Compliance Mode State, 11: Link is in the Test Mode State, 12-14: Reserved, 15: Link is in the Resume State. Note: The Port Link State Write Strobe (LWS) shall also be set to '1' to write this field. This field is undefined if PP = '0'. Note: Transitions between different states are not reflected until the transition is complete. Refer to section 4.19 of xHCI specification for PLS transition conditions. Refer to sections 4.15.2 and 4.23.5 for more information on the use of this field

  • PORTSC1USB3 field descriptions
0 Kudos
Reply
954 Views
YukioOyama
Contributor III

Hi joanxie-san,

Thanks for your reply.

You guided me through the register settings, doesn't that mean it automatically transitions to compliance mode?

Best Regards,

Yukio Oyama

0 Kudos
Reply
948 Views
joanxie
NXP TechSupport
NXP TechSupport

yes, I think so, you can use memtool to read this register to double check if bsp set to the compliance mode or not as default

0 Kudos
Reply
944 Views
YukioOyama
Contributor III

Hi joanxie -san,

Thanks for the quick reply.

I understood about the possibility of not transitioning automatically .

I can understand your suggestion to check the default behavior of the device to find out. However, I will take that test at an outside testing house. (because the measuring equipment to test it is very expensive and not available to us)

I will consider trying it pseudo.

It looks like I can make the transition to compliance mode with a 50 ohm termination and no response to LFPS.

I will open a new case if new questions arise. I'll close this case. Thanks.

Best Regards,

Yukio Oyama

0 Kudos
Reply