URGENT : Changing DRIVE STRENGTH of DDR3 (MR1) via MRS commands

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URGENT : Changing DRIVE STRENGTH of DDR3 (MR1) via MRS commands

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titusstalin
Contributor V

Dear All,

As we are validating the DDR3 read and write burst, we could see failures in DQS output slew rate (SRQdiff) and data output slew rate (SRQ-se).

So, we are thinking to change the drive strength of DDR3 through MRS commands (MR1 register : M5&M1).

To enable/modify the DDR drive strength, we have modified the "flash_headers.S" from u-boot,

MXC_DCD_ITEM(75,MMDC_P0_BASE_ADDR + 0x01C, 0x00048031)

to

MXC_DCD_ITEM(75,MMDC_P0_BASE_ADDR + 0x01C, 0x00048011)

Then I'm not able to get any prints on tera term, its just completely hang.

Can anyone suggest on what to do for making DDR3 passing JEDEC standard and how to change the DDR drive strength for DDR3 and where & which file need to change .

PS: We have calibrated and written given calibrated data from DDR stress test tool.

Thanks for your support.

Regards,

S.Titus

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Titus

for DDR drive strength changing one needs to modify MR1 register

register MMDCx_MDSCR, CMD_BA=1 with CMD_ADDR (bits 31-16)

set to Definition Mode Register 1 (MR1) given in DDR3 datasheet,

for example for MT41K128M16JT :

MR1.jpg

so bits (M5, M1) will be bits (21,17) MMDCx_MDSCR

Best regards

igor

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hermann_ruckerb
Contributor II

Hi,

just one comment:

usually DQS and DQ output slew rate are referring to the DRAM output slew rate. This is measured on a special testboad, but not in the system.

Even if this would be controller in this case I don't think it makes sense to do this measurement in the system environment.

The DRAM and Controller vendor have to ensure that their devices fulfill the Output specs.

Unforunatelly the Scope Compliance tools call the Tests "Read Tests", but these are Data output tests and are not to be performed in the system.

I can help you to do and understand your tests and settings, but I can not help you how to change the settings ..

Hermann

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