UART 8250 into FPGA

[abelussi]

Hi

I implement a UART into my FPGA, compatibles with the serial 8250.

By EIM bus I'll try to see it under "/dev/" as linux driver.

In the device driver file i put the following setting :

uartfpga1@08000000 {
compatible = "ns8250";
reg = <0x08000000 0x20>;
clock-frequency = <80000000>;
status = "okay";
};

&weim {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_weim_fpga_1 &pinctrl_weim_cs0_1 &pinctrl_weim_cs1_1>;
   #address-cells = <2>;
   #size-cells = <1>;
   ranges = <0 0 0x08000000 0x04000000>;
   status = "okay";
   dummy@0,0 {
   reg = <0 0 0x04000000>;
   fsl,weim-cs-timing = <0x00610089 0x00001002 0x1c072000 0x00000000 0x1ce92480 0x00000000>;
   };
};

In the defconfig file i put the following setting:

# Serial drivers #
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_DMA=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_NR_UARTS=1 
CONFIG_SERIAL_8250_RUNTIME_UARTS=1 
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y

The result is that under /dev/ I find ttyS0:

But when I try to write something it is not works

   strace echo -ne "Ciao" > /dev/ttyS0

Do I forget any other setting ?

Thanks in advanced

Antonio

[igorpadykov]

Hi Antonio

please check eim signals with oscilloscope and adjust

uart 8250 timings (checking with its datasheet) and tweaking eim registers

EIM_CSnGCR, EIM_CSnWCR. In dts file these corresponds to

   fsl,weim-cs-timing = <0x00610089 0x00001002 0x1c072000 0x00000000 0x1ce92480 0x00000000>

May be convenient to set these registers using baremetal sdk (zip can be found on below link).

SMP Enable in IMX6 

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[abelussi]

Hi Igor 

Before to check the signals (wr/rd , lba, etc), I think that the problem is that the uart is not instanced properly, in fact as you see the ERROR result below at the different commands:

cat /proc/tty/driver/serial

serinfo:1.0 driver revision:
0: uart:unknown port:00000000 irq:0

strace echo "HELLO" > /dev/ttyS0

execve("/bin/echo", ["echo", "HELLO"], [/* 15 vars */]) = 0
brk(NULL) = 0x185a000
uname({sysname="Linux", nodename="inventami", ...}) = 0
mmap2(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x76f57000
access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory)
open("/etc/ld.so.cache", O_RDONLY|O_CLOEXEC) = 3
fstat64(3, {st_mode=S_IFREG|0644, st_size=42165, ...}) = 0
mmap2(NULL, 42165, PROT_READ, MAP_PRIVATE, 3, 0) = 0x76f4c000
close(3) = 0
open("/lib/tls/v7l/neon/vfp/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/tls/v7l/neon/vfp", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/tls/v7l/neon/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/tls/v7l/neon", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/tls/v7l/vfp/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/tls/v7l/vfp", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/tls/v7l/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/tls/v7l", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/tls/neon/vfp/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/tls/neon/vfp", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/tls/neon/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/tls/neon", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/tls/vfp/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/tls/vfp", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/tls/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/tls", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/v7l/neon/vfp/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/v7l/neon/vfp", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/v7l/neon/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/v7l/neon", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/v7l/vfp/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/v7l/vfp", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/v7l/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/v7l", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/neon/vfp/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/neon/vfp", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/neon/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/neon", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/vfp/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat64("/lib/vfp", 0x7ea7b718) = -1 ENOENT (No such file or directory)
open("/lib/libc.so.6", O_RDONLY|O_CLOEXEC) = 3
read(3, "\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0(\0\1\0\0\0\254n\1\0004\0\0\0"..., 512) = 512
fstat64(3, {st_mode=S_IFREG|0755, st_size=1214096, ...}) = 0
mmap2(NULL, 1283440, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x76df0000
mprotect(0x76f15000, 61440, PROT_NONE) = 0
mmap2(0x76f24000, 12288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x124000) = 0x76f24000
mmap2(0x76f27000, 9584, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x76f27000
close(3) = 0
mmap2(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x76f4b000
set_tls(0x76f4b4c0, 0x76f4bb98, 0x76f5a050, 0x76f4b4c0, 0x76f5a050) = 0
mprotect(0x76f24000, 8192, PROT_READ) = 0
mprotect(0x76f59000, 4096, PROT_READ) = 0
munmap(0x76f4c000, 42165) = 0
brk(NULL) = 0x185a000
brk(0x187b000) = 0x187b000
fstat64(1, {st_mode=S_IFCHR|0660, st_rdev=makedev(4, 64), ...}) = 0
ioctl(1, TCGETS, 0x7ea7bb24) = -1 EIO (Input/output error)
write(1, "HELLO\n", 6) = -1 EIO (Input/output error)
close(1) = 0
write(2, "echo: ", 6echo: ) = 6
write(2, "write error", 11write error) = 11
write(2, ": Input/output error", 20: Input/output error) = 20
write(2, "\n", 1
) = 1
exit_group(1) = ?
+++ exited with 1 +++

[abelussi]

Another information is that when I access to a FPGA memory it works, I can write and read a memory address (0x08000194 for example)