U-BOOT hang after LPDDR4 calibration timing update

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U-BOOT hang after LPDDR4 calibration timing update

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matteo_silotto
Contributor II

Hi,

I'm working on a custom design with the i.MX8M Mini processor.
I successfully completed the RAM calibration process on many boards, and I'm working to integrate the new values on U-Boot lpddr4_timing.c source file.

I have updated all the values obtained from the DDR calibration tool, exept for the following two entry:

   { 0x3d4020f4, 0xc99 }
   { 0x3d4030f4, 0xc99 }

When I add these two values on lpddr4_timing.c the U-Boot SPL hangs after the DRAM init procedure.

On the original lpddr4_timing.c source file these two registers are not listed (unlike all other registers that are already present).

I can't find on the reference manual any information about these.

Please help me to know the meaning of these registers and if they need to be updated for the correct integration of calibration results.

Thanks.

Best regards,

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5 Replies

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weidong_sun
NXP TechSupport
NXP TechSupport

Hello Matteo,

See below, please! 

-----------------------

0x3d4020f4 and 0x3d4030f4 are the regster addresses of RANKCTL for frquency point1 and frequency point2, which have the same meanning of RANKCTL (0x3d4000f4). You can find the definition in RPA tool.

 

For i.MX8MM,  it has the extra two registers while i.MX8MQ doesn't.

 

Regarding your  issue,

1. Which CPU does you use , imx8M mini or 8MQ?

2. How many ranks (chip select) does your board have?

3. What is the code base?

 

If you can pass calibration and stress test in DDR tool, I'm curious why it would fail in uboot.

------------------------------

Have  a nice day!

B.R,

Weidong

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matteo_silotto
Contributor II

Hello Weidong,
thanks for the clarification.

About your questions:

  1. I'm using an i.MX8M Mini (MIMX8MM6CVTKZAA)
  2. I'm using the same LPDDR4 part number used on EVK (MT53D512M32D2DS) with dual-channel single chip select
  3. U-Boot rel_imx_4.19_35_1.1.0

To be clear: I'm able to successfully complete the calibration and stress test with the NXP DDR calibration tool. I'm also able to build and run the EVK U-Boot (rel_imx_4.19_35_1.1.0) and also our U-Boot (with some minor changes on code). Now, I'm trying to update the lpddr4_timing.c with the output of the calibration process, and I have already included all value changes except for the two indicated. With all other changes, U-Boot continues to start correctly but it hangs only when I add the settings for 0x3d4020f4 and 0x3d4030f4.

Are these two register settings necessary? I see that they are not present on the EVK lpddr4_timing.c file.

Thanks.

Best regards,

Matteo Silotto

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weidong_sun
NXP TechSupport
NXP TechSupport

Hi Matteo,

you are using i.MX8M MINI, these 2 registers are not configured in lpddr4_timing.c in default bsp, so actually for your board, you don't need to configure them.  so you can't remove it from lppdr4_timing.c , and try to boot you board.

Have a nice day!

B.R,

Weidong

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matteo_silotto
Contributor II

Hi Weidong,

thanks for your clarification. I'm are able to correctly boot the board.

Best regards,

Matteo Silotto

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weidong_sun
NXP TechSupport
NXP TechSupport

OK, good job!

you are welcome!

Have a nice day!

B.R,

weidong

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