Typo in Linux drivers/clk/imx/clk-imx8ulp.c related to PCC5 and CGC2

[gfrung]

There's a typo in the definition of pcc5_periph_bus_sels in drivers/clk/imx/clk-imx8ulp.c lines 30 through 32, see here.

static const char * const pcc5_periph_bus_sels[] = { "dummy", "dummy", "lposc",
						     "sosc_div2", "frosc_div2", "lpav_bus_clk",
						     "pll4_vcodiv", "pll4_pfd3_div1", };

Specifically, as PCC5 is connected to CGC2, sosc_div2 should be cgc2_sosc_div2 and frosc_div2 should be cgc2_frosc_div2, like this:

static const char * const pcc5_periph_bus_sels[] = { "dummy", "dummy", "lposc",
						     "cgc2_sosc_div2", "cgc2_frosc_div2", "lpav_bus_clk",
						     "pll4_vcodiv", "pll4_pfd3_div1", };

These clocks are defined in imx8ulp_clk_cgc2_init on lines 287 through 299, see here.

clks[IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE] = imx_clk_hw_gate_dis("cgc2_sosc_div1_gate", "sosc", base + 0x108, 7);
clks[IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE] = imx_clk_hw_gate_dis("cgc2_sosc_div2_gate", "sosc", base + 0x108, 15);
clks[IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE] = imx_clk_hw_gate_dis("cgc2_sosc_div3_gate", "sosc", base + 0x108, 23);
clks[IMX8ULP_CLK_CGC2_SOSC_DIV1] = imx_clk_hw_divider("cgc2_sosc_div1", "cgc2_sosc_div1_gate", base + 0x108, 0, 6);
clks[IMX8ULP_CLK_CGC2_SOSC_DIV2] = imx_clk_hw_divider("cgc2_sosc_div2", "cgc2_sosc_div2_gate", base + 0x108, 8, 6);
clks[IMX8ULP_CLK_CGC2_SOSC_DIV3] = imx_clk_hw_divider("cgc2_sosc_div3", "cgc2_sosc_div3_gate", base + 0x108, 16, 6);

clks[IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE] = imx_clk_hw_gate_dis("cgc2_frosc_div1_gate", "frosc", base + 0x208, 7);
clks[IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE] = imx_clk_hw_gate_dis("cgc2_frosc_div2_gate", "frosc", base + 0x208, 15);
clks[IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE] = imx_clk_hw_gate_dis("cgc2_frosc_div3_gate", "frosc", base + 0x208, 23);
clks[IMX8ULP_CLK_CGC2_FROSC_DIV1] = imx_clk_hw_divider("cgc2_frosc_div1", "cgc2_frosc_div1_gate", base + 0x208, 0, 6);
clks[IMX8ULP_CLK_CGC2_FROSC_DIV2] = imx_clk_hw_divider("cgc2_frosc_div2", "cgc2_frosc_div2_gate", base + 0x208, 8, 6);
clks[IMX8ULP_CLK_CGC2_FROSC_DIV3] = imx_clk_hw_divider("cgc2_frosc_div3", "cgc2_frosc_div3_gate", base + 0x208, 16, 6);

The consequence of this typo is that clocks <&cgc2 IMX8ULP_CLK_CGC2_SOSC_DIV2> and <&cgc2 IMX8ULP_CLK_CGC2_FROSC_DIV2> don't work in device trees, resulting in an error during boot that "clk: failed to reparent xxx to cgc2_frosc_div2: -22", because the driver thinks that is not a valid clock when it is.  Correcting the typo in the driver allows the clock to be configured and everything works fine.

Thanks for your time looking into this!