Hello Everyone
Does i.MX.8M.Mini support TwinDie LPDDR4?
TwinDie requires additional DG1 for addressing x8 and ZQ.
Thanks
To be exact it is not related to the number of dies. Modern LPDDR4 use 4 or sometimes even 8 dies per component! Important for you is just that you correctly wire the address, bank, bank group and chip-select lines.
The largest LPDDR4 device currently on the market as 64Gbit (=8 GB!) and comes from Micron: https://www.memorydistri.com/mt53e2g32d4dt-046%20wt:a.html
Other manufacturers like Samsung, Hynix, Nanya go to maximum 32Gbit with their LPDDR4 and only offer the big 64Gb size on LPDDR4X (with lower I/O voltage of 0.6V) only. As I understand the i.MX8 processors are not able to operate LPDDR4X, but only LPDDR4.
@IvanCa
Hello,
Looks like You mean signals BG0/1 for DDR4. Use Table 16 (DDR3L/LPDDR4/DDR4 connectivity)
of Hardware Development Guide for the i.MX8Mm:
https://www.nxp.com/webapp/Download?colCode=IMX8MMHDG
Regards,
Yuri.
Hello Yurii
Right, it is BG0/1, typo. But the question is still up. In case I use TwinDie DDR memory I can use only one memory controller of iMX8MINI (MIMX8MM5DVTLZAA). To use two TwinDie chips/controllers I need two extra bits of the Bank Group (BG) signals to address other memory groups on the second memory chip?
Thanks, Ivan
@IvanCa
Hello,
Customers can use i.MX8Mn DDR4 design as an example.
https://www.nxp.com/downloads/en/schematics/8MNANOD4-EVK-DF-SCH.7z
Regards,
Yuri.
Hello Yurii.
Reference design schematic, you guess I can add one more DDR4 device since BG0 and BG1 are engaged?
Thanks
It seems I got the idea already.
Thanks Yurii
@IvanCa
Hello,
Basically connection scheme for DDR4 is shown in the Table 16 (DDR3L/LPDDR4/DDR4
connectivity). Signals BG0 and BG1 are shown there.
But we have not tested an example for the case with BG1 using.
Regards,
Yuri.