Trying to solve the mystery of NO uSDHC command response or interrupts

[shefft]

2i.MX6 SDL

I’m seeing a strange problem with the SD card interface on a new board we are bringing up.  In Uboot, the board hangs on a “mmc dev 0” init command.  It turns out that the command response is never received to the second command that is issued (CMD8).  As a result, the uSDHCx_PRES_STATE register shows the Command Inhibit bit is set, there is nothing in the four uSDHCx_CMD_RSP regs, and no interrupt is generated.  There is an interrupt received and no problem seen with the very first issued command, a CMD0 (go to idle I think?).  I’ve tried multiple cards and get the same result. We’ve also scoped the SD_CLK and SD_CMD lines as a sanity check, and although I haven’t analyzed the CMD line we do see some activity on there.

I have a Nitrogen6x reference board which works fine. Both boards are using uSDHC3 and the interface connections are identical, with the exception of the specific GPIO pin used for Card Detect, and the addition of a Write Protect pin.  I’ve made the needed CD change and it looks to be working just fine – wouldn’t get this far in the code without detecting the card properly.  As per the WP, the NitrogenLite version of the board which I also reference does not have one, so I have ignored it.

Here is the register readout for both of these commands, and also a compare to a Nitrogen6x board register readout (which works fine for the SD card).  This readout is taken right after the transfer type write in the Uboot mmc driver esdhc_send_cmd function in fsl_esdhc.c.

/* Send the command */

esdhc_write32(&regs->cmdarg, cmd->cmdarg);

esdhc_write32(&regs->mixctrl,(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));

esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);

reg dump for my board:

CMD_SEND:0

ARG 0x00000000

esdhc_send_cmd: sd regs base=2198000, &irqstat=0x2198030, irqstat=0x1

esdhc_send_cmd: sd regs addr=2198000, value=0x0

esdhc_send_cmd: sd regs addr=2198004, value=0x10000

esdhc_send_cmd: sd regs addr=2198008, value=0x0

esdhc_send_cmd: sd regs addr=219800c, value=0x0

esdhc_send_cmd: sd regs addr=2198010, value=0x0

esdhc_send_cmd: sd regs addr=2198014, value=0x0

esdhc_send_cmd: sd regs addr=2198018, value=0x0

esdhc_send_cmd: sd regs addr=219801c, value=0x0

esdhc_send_cmd: sd regs addr=2198020, value=0x0

esdhc_send_cmd: sd regs addr=2198024, value=0xff8d8088

esdhc_send_cmd: sd regs addr=2198028, value=0x800020

esdhc_send_cmd: sd regs addr=219802c, value=0x8e10ff

esdhc_send_cmd: sd regs addr=2198030, value=0x1

esdhc_send_cmd: sd regs addr=2198034, value=0x157f510f

esdhc_send_cmd: sd regs addr=2198038, value=0x0

esdhc_send_cmd: sd regs addr=219803c, value=0x0

esdhc_send_cmd: sd regs addr=2198040, value=0x7f30000

esdhc_send_cmd: sd regs addr=2198044, value=0x8100810

MMC_RSP_NONE

mmc_start_init: reset complete

CMD_SEND:8

ARG 0x000001AA

esdhc_send_cmd: sd regs base=2198000, &irqstat=0x2198030, irqstat=0x0

esdhc_send_cmd: sd regs addr=2198000, value=0x0

esdhc_send_cmd: sd regs addr=2198004, value=0x10000

esdhc_send_cmd: sd regs addr=2198008, value=0x1aa

esdhc_send_cmd: sd regs addr=219800c, value=0x81a0000

esdhc_send_cmd: sd regs addr=2198010, value=0x0

esdhc_send_cmd: sd regs addr=2198014, value=0x0

esdhc_send_cmd: sd regs addr=2198018, value=0x0

esdhc_send_cmd: sd regs addr=219801c, value=0x0

esdhc_send_cmd: sd regs addr=2198020, value=0x0

esdhc_send_cmd: sd regs addr=2198024, value=0xff8d8009

esdhc_send_cmd: sd regs addr=2198028, value=0x800020

esdhc_send_cmd: sd regs addr=219802c, value=0x8e10ff

esdhc_send_cmd: sd regs addr=2198030, value=0x0

esdhc_send_cmd: sd regs addr=2198034, value=0x157f510f

esdhc_send_cmd: sd regs addr=2198038, value=0x0

esdhc_send_cmd: sd regs addr=219803c, value=0x0

esdhc_send_cmd: sd regs addr=2198040, value=0x7f30000

esdhc_send_cmd: sd regs addr=2198044, value=0x8100810

------ HANGS HERE ------------

/* Wait for the command to complete */

while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)));

reg dump for nitrogen:

CMD_SEND:0

ARG 0x00000000

esdhc_send_cmd: sd regs base=219c000, &irqstat=0x219c030, irqstat=0x1

esdhc_send_cmd: sd regs addr=219c000, value=0x0

esdhc_send_cmd: sd regs addr=219c004, value=0x10000

esdhc_send_cmd: sd regs addr=219c008, value=0x0

esdhc_send_cmd: sd regs addr=219c00c, value=0x0

esdhc_send_cmd: sd regs addr=219c010, value=0x0

esdhc_send_cmd: sd regs addr=219c014, value=0x0

esdhc_send_cmd: sd regs addr=219c018, value=0x0

esdhc_send_cmd: sd regs addr=219c01c, value=0x0

esdhc_send_cmd: sd regs addr=219c020, value=0x0

esdhc_send_cmd: sd regs addr=219c024, value=0xff8d8088

esdhc_send_cmd: sd regs addr=219c028, value=0x800020

esdhc_send_cmd: sd regs addr=219c02c, value=0x8e10ff

esdhc_send_cmd: sd regs addr=219c030, value=0x1

esdhc_send_cmd: sd regs addr=219c034, value=0x157f510f

esdhc_send_cmd: sd regs addr=219c038, value=0x0

esdhc_send_cmd: sd regs addr=219c03c, value=0x0

esdhc_send_cmd: sd regs addr=219c040, value=0x7f30000

esdhc_send_cmd: sd regs addr=219c044, value=0x8100810

MMC_RSP_NONE

mmc_start_init: reset complete

CMD_SEND:8

ARG 0x000001AA

esdhc_send_cmd: sd regs base=219c000, &irqstat=0x219c030, irqstat=0x1

esdhc_send_cmd: sd regs addr=219c000, value=0x0

esdhc_send_cmd: sd regs addr=219c004, value=0x10000

esdhc_send_cmd: sd regs addr=219c008, value=0x1aa

esdhc_send_cmd: sd regs addr=219c00c, value=0x81a0000

esdhc_send_cmd: sd regs addr=219c010, value=0x1aa

esdhc_send_cmd: sd regs addr=219c014, value=0x0

esdhc_send_cmd: sd regs addr=219c018, value=0x0

esdhc_send_cmd: sd regs addr=219c01c, value=0x0

esdhc_send_cmd: sd regs addr=219c020, value=0x0

esdhc_send_cmd: sd regs addr=219c024, value=0xff8d8088

esdhc_send_cmd: sd regs addr=219c028, value=0x800020

esdhc_send_cmd: sd regs addr=219c02c, value=0x8e10ff

esdhc_send_cmd: sd regs addr=219c030, value=0x1

esdhc_send_cmd: sd regs addr=219c034, value=0x157f510f

esdhc_send_cmd: sd regs addr=219c038, value=0x0

esdhc_send_cmd: sd regs addr=219c03c, value=0x0

esdhc_send_cmd: sd regs addr=219c040, value=0x7f30000

esdhc_send_cmd: sd regs addr=219c044, value=0x8100810

MMC_RSP_R1,5,6,7         0x000001AA

mmc_send_if_cond: send com completed, err=0

mmc_start_init: ver test complete

------- CONTINUES ON FINE FROM HERE --------------

Have you ever seen anything like this before?  What else could you suggest I possibly do in SW to debug this, seeing as how the registers just appear to shut down?  The reason I say that is because one other very strange thing about this is that the CTOE timeout bit in the uSDHCx_INT_STATUS never gets set during the IRQ wait, even though it sounds like it should – “if no response is returned within 64 SDCLK cycles from the end bit of the command”

[igorpadykov]

Hi Tyler

you can check hardware with CMD8 using SDK usdhc test:

i.MX 6Series Platform SDK : Bare-metal SDK for the i.MX 6 series

regarding Nitrogen6x interrupt I would suggest to post this on dedicated

to this board forum, since this may be specific software implementation issue

http://boundarydevices.com/community/

Best regards

igor

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[shefft]

2

2

Hi Igor,

unfortunately it's looking suspiciously like the same problem occurring running the SDK.  I'm going to dive deeper to see if it is in fact the same result.

---- Running uSDHC test, type 'x' to exit.

Make sure to insert an MMC/SD card into SD slot #3

Please select test:

        0 - usdhc polling IO

        1 - usdhc ADMA polling

        2 - usdhc ADMA interrupt

        x - to exit.

1. Init card.

   Card on SD3 is inserted.

   Card on SD3 is not write protected.

Reset card.

Send CMD0.

Send CMD8.

Command timeout.

Error status: 0x0

Command timeout.

Error status: 0x0

Send ACMD41.

Command timeout.

Error status: 0x0

Send CMD55 failed.

Command timeout.

Error status: 0x0

Send CMD1 failed.

UCMD1 failed.

SD/MMC initialize failed.

usdhc polling IO test FAILED.

[igorpadykov]

Hi Tyler

seems smth wrong wih board, one can check

signals with oscilloscope and compare with good (Nitrogen6x)

case.

Best regards

igor

[shefft · Accepted solution]

2

Hi Igor,

I was given to understand that the signalling had already been verified by another engineer, but I discovered that the CMD and CLK line levels were too low, so turned out to be a HW problem.

best regards