To improve i.MX6Q SDMA performance for ESAI read access.

[satoshishimoda]

Hi community,

I want to your advice about i.MX6Q SDMA.

Our partner is using i.MX6Q SDMA for ESAI on a custom board, but its performance is not enough currently.

In fact, they want to over 54 FIFOs read access from ESAI when Fs=48kHz, but now SDMA seems to not be able to handle over 54 FIFOs read access.

So we want to information how to improve SDMA performance.

Please see their environment and our questions as below.

=====

[Environment]

chip: i.MX6Q

DRAM: DDR3 528MHz 64-bit

CCM: Default as Linxu BSP (L3.0.35_4.1.0)

=====

[Q1]

They are using app_2_mcu for ESAI now, but shp_2_mcu seems faster than app_2_mcu.

Should they use shp_2_mcu instead of app_2_mcu to improve SDMA performance?

[Q2]

If the answer to Q1 is "YES", would you let me know whether Linux BSP (L3.0.35_4.1.0) supports shp_2_mcu for ESAI?

[Q3]

Could you give me advice to improve SDMA transfer performance other than using shp_2_mcu?

(e.g. They should increase the number of Buffer Description, they should write the data from ESAI to on on chip SRAM instead of DRAM, etc...)

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

1. one needs to use shp_2_mcu since ESAI is connected to

SPBA bus of SDMA

2. Linux BSP (L3.0.35_4.1.0) supports shp_2_mcu for ESAI

3. in general SDMA performance depends on others bus masters

activities : arm core, vpu,ipu, gpu. So it is recommended to decrease

their activity by reducing number accesses from vpu,ipu, gpu, probably

decreasing fps, resolution/bpp numbers. One can try also to use iRAM, however

improvement may depend on use case. More straightforward method,

changing bus priorities is not recommended/supported since requires NIC-301

programming. Just for reference one can look at sect.45.4.3.1 "QoS registers'

address look-up example", sect.44.5.1.1 "Arbitration General" IMX6DQRM

Best regards

igor

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