To apply spectrum spread to i.MX6 IPU1_DI0_CLK.

[satoshishimoda]

Hi community,

I have a question about i.MX6SDL PLL2 spread spectrum.

A end user is trying to apply the spread spectrum to LCD clock.

We think spread spectrum is applied to PLL2 PFD clock when PLL2 spread spectrum is valid.

And now, the spread spectrum works well on DDR clock line, but does not work well on LCD clock line (IPU1_DI0_CLK) even though LCD clock is provided from PLL2 PFD.

Please see the detail as below.

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[BSP]

L3.0.35_4.1.0

[Clock route]

1. osc_clk(24MHz) --> pll2_528_bus_main_clk(528MHz) --> pll2_pfd_400MHz(396MHz) --> ipu1_di0_clk (132MHz)

2. ocs_clk(24MHz) --> pll2_528_bus_main_clk(528MHz) --> pll2_pfd_400MHz(396MHz) --> periph_clk(396MHz) --> mmdc_ch0_axi_clk(396MHz) --> ipu1_di0_clk(132MHz)

[Clock route setting file]

File: arch/arm/mach-mx6/clock.c

Function: clk_set_parent() in mx6_clocks_init() function.

[Waveform(attached file)]

DDR clock : ddr_clk.jpg ==> spectrum spread works well.

LCD clock : lcd_clk_2.jpt ==> spectrum spread does not work well. (sorry for hard to see)

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[Question]

Is some additional setting required to apply spread spectrum to IPU1_DI0_CLK?

And if there is a wrong in our understanding, please tell me it.

Best Regards,

Satoshi Shimoda

[igorpadykov]

Actually you can observe some kind of digital filtering

when dividing PLL2 frequency 528MHz (T=1.9nS period),

with for example jitter 1%  deltaT=+-20pS to LCD 10MHz, Tlcd=100nS.

Very simply speaking CCM/IPU just digitally divide incoming PLL2

frequency so Tlcd=sum of 50 PLL2 clocks, due to random

nature of jitter sum of 50  deltaT=+-20pS will not lead

to +-deltaTlcd=50*20pS= 1ns, instead they probably

are filtered (summing and compensate each other) with probably the

same deltaTlcd=deltaT=+-20pS as it came in input.

[satoshishimoda]

Hi chipexpert,

Actually, the user is using the below setting.

And the LCD clock waveform when 10ns/div is the attached file.

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DDR clock = 396MHz (T=2.525 ns period)

Spread Spectrum = -5% => deltaT = 2.525 * 0.05 = 0.126 ns

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We cannot see the delta even if the scale is 10ns/div also, but the reason is a low number of the clock cycle, is this right?

Best Regards,

Satoshi Shimoda

[igorpadykov]

You are using the same clock as input for both clocks: pll2_pfd_400MHz(396MHz)

so obviously spread spectrum is present on both outputs clocks IPU1_DI0_CLK and

ddr_clk. Problem may be with interpretation: lcd_clk is scaled down by x10 (100ns/div vs 10 ns/div).

So visually you interpret is as "not work well". However spread spectrum still is present here.