I would like to use the UART feature of the i.MX6 for having a RS-485 driver connection, as per Figure 64-11 of the reference manual.
The goal is to drive the direction control (DREN) of a half-duplex transceiver under timing constraint.
Can you please confirm that in such a connection and with appropriate register setup, the UART is able to automatically handle the CTS_B pin upon transmit?
Is there documentation showing the timing diagram of the CTS_B signal with respect to the end of a transmit?
In other words, what is the timing (maximum delay) between the stop bit of the last transmitted byte and the release of the CTS_B in this automatic mode?
I have followed up this question with the distributor supporting you.
There are ways to handshake RTS/CTS for half duplex communication but your specific question is about CTS_B ability to automatically configure external RS485 tranceiver direction (as shown in Figure 64-11. RS-485 driver connection). This is done by software using UCR2 as described in RS485 the programming exemple (chapter 64.13.2). We advertise this feature because it is more convient to access that uart register bit than changing pinmux / direction to access the I/O but I don't see any automatic way of toggling it in this mode.
Concerning the linux implementation of the RS485 driver, you might have a look at this other thread : https://community.freescale.com/thread/312742
Best regards, Philippe.
Yes, we can confirm that CTS_B it is automatically handle, since this output pin serves two purposes. Normally, the receiver indicates that it is ready to
receive data by asserting this pin (low). When the CTS trigger level is programmed to trigger at 32 characters received and the receiver detects the valid start bit of the 33 character, it de-asserts this pin. The operation of this output is the same regardless of whether the UART is in DTE or DCE mode.
For timings you can check the Datasheet and review the External Peripheral Interface Parameters,
Transmit Bit Time tTbit 1/Fbaud_rate – Tref_clk
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
1/Fbaud_rate + Tref_clk