Timing/Delay adjustment in iMX8M for LPDDR4

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Timing/Delay adjustment in iMX8M for LPDDR4

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Contributor II

Hi,

I am working on iMX8M based custom board. We have interfaced LPDDR4 with iMX8M processor. 

We did the Post Reflection simulation on our board. We haven't run timing/delay simulation. 

Can we adjust the signal timing/delay at processor side using firmware? Please provide reference for the same.  

Thanks.

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NXP TechSupport
NXP TechSupport

Hi Ritesh

I am afraid it is not possible, as there is no dcd structure in u-boot like i.MX6/7 series.

DDR controller uses firmware (its sources are not available) and ddr goes through training

to be usable. Uboot spl manages loading ddr controller firmware and training process.

For avoiding reflections recommended to follow hardware guide available on

i.MX 8M Applications Processor | Arm® Cortex®-A53, Cortex-M4 | 4K display resolution | NXP 

Best regards
igor
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Contributor I

Hi Igor

I have a similar question which seems to have been answered already, but let me make sure.

I am wondering if I could get the DRAM data eye pattern with firmware programing, scanning DQS to DQ delay which could be done within PHY functionality and scanning VREF.  Is it also impossible? I noticed the PHY registers region assigned in the M4/A53 memory map space but there are no detail descriptions and readouts looks ALL "0"s even after calibration. 

If it is not possible, is there any other way to check the SI margin between DDR and the Processor without a scope?

Regards,

Ken

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