Theoretical dual display size of iMX6QP

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Theoretical dual display size of iMX6QP

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torus1000
Contributor V

Hi,

I just want to know the theoretical limitation of IPU or MMDC.

An i.MX6QP demo support 8 layers overlay of 1920x1080@60fps.
  https://community.nxp.com/docs/DOC-106439
  https://community.nxp.com/docs/DOC-328293

Is it theoretically OK to display HDMI and LVDS simultaneously if each of them has 4 layers of 1920x1080@60fps ?

Can anyone help me?

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joanxie
NXP TechSupport
NXP TechSupport

I don't think mx6qp can suppor this, for overlay, which depends on vpu, vpu can support up to 8 D1@30fps.

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torus1000
Contributor V

Dear Joan joanxie

Thank you for replying.

I think vpu is typo of gpu which support multi-layer overlay.

BTW I found actual rate as following.

  https://community.nxp.com/message/452579
   DDR3-1066 32-bit reaches a maximum of ~2.5 GB/s in total (theoretic 4.2 GB/s)
   DDR3-1066 64-bit reaches a maximum of ~2.8 GB/s in total (theoretic 8.5? GB/s)

My expectation is improved 40% (~4.0 GB/s in total) to use PRE in i.MX6QP.
If it true, fullHD-dual display(2x1920x1080x60/s=250MP/s) may possible for only 2 layer overlay implementation.

250MP/s x2 x4B/Pix =2GB/s          //half of 4GB/s

I think it' not bad. How do you think?

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