The side effect/impact of SSC(Spectrum Spread) on PLL2.

[asou_junichi]

SSC(Spectrum Spread) is enabled and only DDR and LVDS use the PLL2 clock.

(PLL2 clock : 396MHz -> 384MHz by 23kHz step)
In the case, are there any side effect/impact to the connected devices to the clock delivered from PLL2?

[asou_junichi]

Hi,

Thank you for an answer.

I got it.

BR,

Jun

[igorpadykov · Accepted solution]

Hi

yes one should consider SSC effect on any devices (modules) using that clock,

in particular for ddr check micron document p.14

http://www.micron.com/~/media/documents/products/data-sheet/dram/ddr3/ddr3l_2gb_graphics_addendum.pd...

Best regards
igor
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