The routing length problem of LPDDR4 of i.MX8DX and i.MX8DXP.

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The routing length problem of LPDDR4 of i.MX8DX and i.MX8DXP.

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Contributor I

Hello:

Regarding the routing length problem of LPDDR4 of i.MX8DX and i.MX8DXP.
1) In the i.MX family, are the LPDDR4 routing length on the SOC equally long? (According to experience, they are generally of unequal length, such as PKG L in the attached table.)
2) If the length is not equal, do i.MX8DX and i.MX8DXP have relevant data? Such as the below image.
LPDDR4 Skew check list.bmp

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NXP TechSupport
NXP TechSupport

Hello 洪福 马,

When performing the required trace length matching for LPDDR4/DDR3L routing, the bond wires within the i.MX8X package need to be accounted for and included in the match calculation. The package trace lengths for each pin will be included on the Hardware Design Guide.

As the i.MX8DX/DXP have not been publicly released I would need to ask you to contact your NXP FAE or Distributor to inquire about this information.

My apologies for the inconvenience.

Regards,

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Contributor I

Hi gusarambula:

Thank you very much, I will contact FAE for relevant information!

Thank you!

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