The level of GPIO on reset state in i.MX6ULL

[shanashiro]

Is it need pull up or pul down GPIO on reset state in i.MX6ULL?

[Yuri]

@shanashiro 
Hello,

  It depends on applications - using external pulling resistors. 
Note, i.MX6ULL pins state during reset (except Boot Mode Configuration
Pins) are not specified. 

  Customers can use use Table 91 (14 x 14 mm Functional Contact Assignments),
column"Out of Reset Condition"

https://www.nxp.com/docs/en/data-sheet/IMX6ULLCEC.pdf

  Also

https://community.nxp.com/t5/i-MX-Processors/about-pin-mode-during-POR-on-i-MX6ULL/m-p/1153519

Regards,
Yuri.

[BiyongSUN]

GPIO is not pin/PAD(IOMUX).

GPIO only has data register, which is logic "0", or "1". 

GPIO, ADC and SAI are equal. 

Please check for the pad/pin Out of Reset Condition in datasheet.

During the reset, it is hi-z.