The function of the i.mx6ull nand flash

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The function of the i.mx6ull nand flash

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yunlai
Contributor I

Hi:

    Why is there no nand flash function to output in i.mx6ull? The boot pin setting is also correct: CFG1[7-0]: 1 0 1 1 0 0 1 1, CFG2[7-0]: 0 0 0 0 0 0 0 0, CFG4[7-0]: 0 0 0 0 0 0 0 0, BMODE[1:0]: 0 1. The software program can be used correctly on another product. The CPU, DDR3, and nand flash circuits on this product are all the same as the other product, except that the PCB layout and layout are different. But changing the nand flash function to GPIO port can output high and low levels. Is it because the power supply of the CPU is routed on the PCB, which causes the flash function to fail or the DMA runs abnormally? So which power supply will cause this phenomenon? Thank you!

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igorpadykov
NXP Employee
NXP Employee

Hi Yuan

 

>The CPU, DDR3, and nand flash circuits on this product are all the same as the

>other product, except that the PCB layout and layout are different

 

if layout is different recommended first run ddr test

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-6-7-DDR-Stress-Test-Tool/ta-p/11082...

then rebuild image with new ddr settings updated in uboot dcd header:

https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/mx6ullevk/imximage.cfg?h=i...

 

Best regards
igor

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michaelyang
Contributor I

HI igor, 

we meet the same issue, also need your support, it is urgent project, tks in advance~

We use the nand flash MT29F32G08CBACAWP. It is found that the CPU cannot output the flash signal. Because the flash port of the CPU can be used as a GPIO function, we used the GPIO function for testing, and the result can output normal high and low levels. But when switching to the flash function, there is still no flash signal output. According to your experience, is it caused by nand flash devices? Or is it caused by PCB line route? Is it necessary to reduce the frequency of nand flash or improve the drive capability of the main control on the flash function? If the nand flash can be read and written correctly in this way, can it be explained that it is caused by the route wiring of the PCB? thank you very much!

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yunlai
Contributor I

HI,Igor:

    Thanks your answer!

     After using the DDR stress test, you need to increase the voltage of VDD_SOC_CAP to 1.25V to pass. The DDR model is the same as the model of another successful product. So I fixed the voltage at 1.3V in uboot. But the flash function still cannot come out. Then we have increased the DSE(Drive Strength) of the flash of CPU, we can read the capacity of the flash, but the GPMI timeout appears when running further down. It is suspected that there is a problem with the DDR, I don't know, right? Is this caused by the PCB route trace of the DDR or caused by the PCB route trace of the FLASH?

    Is there any way to run DDR normally on the current PCB board? For example, what settings are changed in the software? DDR frequency? DDR Drive capability? CPU frequency?...

    Thanks!

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igorpadykov
NXP Employee
NXP Employee

if there is need for changing VDD_SOC_CAP, this may point to power supplies issues.

May be suggested to check power supplies using Hardware Development Guide for the i.MX 6ULL Applications Processor

 

Best regards
igor

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yunlai
Contributor I

Hi,igor:

    Thanks your reply!

    Is there any software method to make the software run on the current board? Such as frequency reduction or what method?

    Thanks!

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yunlai
Contributor I

HI,Igor:

    Thanks your answer!

     After using the DDR stress test, you need to increase the voltage of VDD_SOC_CAP to 1.25V to pass. The DDR model is the same as the model of another successful product. So I fixed the voltage at 1.3V in uboot. But the flash function still cannot come out. We have increased the drive capacity of the flash, which can read the capacity of the flash, but the GPMI timeout appears when running further down. It is suspected that there is a problem with the DDR, I don't know, right? There is also the improvement of the flash drive ability to read the flash chip. Is this caused by the PCB route trace of the DDR or caused by the PCB route trace of the FLASH?

    Is there any way to run DDR normally on the current PCB board? For example, what settings are changed in the software? DDR frequency? DDR Drive capability? CPU frequency?...

    Thanks!

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