The dma_rx_callback function on the IMX6ULL chip is being executed less frequently than expected

[JanieZee]

Hello, I have encountered an issue with the UART on the IMX6ULL chip, and I would appreciate your help in resolving it. I am using UART5 with both RX and TX configured to use DMA. The ICD is set to 3, which corresponds to 32 frames, IDDMAEN is enabled, RXDMAEN is enabled, ATDMAEN is enabled, and RXTL is set to 16. On the RX signal line, 9 bytes are transmitted, followed by 10 bytes after a 2.5 ms interval. However, the dma_rx_callback function indicates that 19 bytes were received. I was expecting the dma_rx_callback function to be triggered twice, once after receiving the 9 bytes and again after receiving the 10 bytes, as the 2.5 ms interval should trigger the DMA RX interrupt twice. But why is the dma_rx_callback function only executed once?

thanks!

[Bio_TICFSL]

Hello,

Perhaps the problem concerns with the fact, that DMA transfer data in bursts, DMA cannot transfer less data, than burst length. The burst size of half of UART FIFO is good choice. 

Regards

[JanieZee]

Thank you for your reply! Based on your suggestions, I made two changes:
1) Changed RXTL_UART from 16 to 7, as the minimum receive frame is 7 bytes;
2) Modified the src_maxburst of the dma rx in the imx_uart_dma_init function from RXTL_UART to RXTL_UART/2.
```
slave_config.direction = DMA_DEV_TO_MEM;
slave_config.src_addr = sport->port.mapbase + URXD0;
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
slave_config.src_maxburst = (RXTL_UART/2);
ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
```
However, I still encounter the same issue, where an interval of 1.8ms between two frames is still considered as one frame. Are there any other changes I should consider?