The HW_PINCTRL_EMI_ODT_CTRL register for i.MX28

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The HW_PINCTRL_EMI_ODT_CTRL register for i.MX28

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Senior Contributor I

Dear all,

I received the question from my customer about the HW_PINCTRL_EMI_ODT_CTRL register for i.MX28.

They need the function which this register has.

However, I cannot find the explanation about this register.

Someone should let me know about this register.

  • Q1)  To which pins does each "Slice" correspond?
  • Q2)  Though it seems that the ODT Calibration can choose "1-step Adjustment" etc., please let me know the function of this register bit.

Best Regards,

George

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NXP TechSupport
NXP TechSupport

  Please look at my comments regarding the issue.

1.
Some details about i.MX28 DRAM Controller settings may be found in comments of

DDR initialization tool :

https://community.freescale.com/docs/DOC-1455

2.

The so called ODT for EMI ADDRESS is not supported on i.MX28.

Please leave associated fields in default state.

  Basically for i.MX28 ODT is not needed to run at the max DRAM frequency of

200MHz for DDR2 or mDDR (even at max temp and worst process). 

Since it is not necessary, we don't recommend using the ODT because it will

result in a significant power increase during DRAM communication.

3.
SLICE0 relates to byte 0 (data, mask, strobe): EMI_D[00:07], EMI_DQM0, EMI_DQS0
SLICE1 relates to byte 1: EMI_D[08:15], EMI_DQM1, EMI_DQS1

SLICE2 and SLICE3 are not used in i.MX28.

Have a great day,
Yuri

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