Supporting single channel LPDDR4 on iMX8MP

[simonng]

Hi NXP,

Can the i.MX8MP processor support 200B LPDDR4 DRAM with only single channel?

If yes, is it channel A or channel B?

Thanks for your help.

[igorpadykov]

Hi Simon

in general it can be supported (channel A). Just for comparison one can look at

i.MX 8M Mini LPDDR4 EVKB Compute Module Design Files

and single channel  Design Files for an i.MX 8M Nano Compute Module with LPDDR4

Best regards
igor

[simonng]

Hi igor,

Are you still looking at this issue? Please help me to follow up.

Regards,

Simon

[simonng]

Hi Igor,

Thanks for your reply. I tried to set the single channel setting and run it on the 8MP EVKB (8MPLUSLPD4-EVK). Then I used the DDR Tool to run the Stress Test. But the test hang up. I noticed that the Col size is changed to 11 and the density per chip select is still 3072MB. I attached the ds file and RPA file. Can you help me to check this problem?

Here is the log:

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 2000MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 16, bank num: 8
Row size: 17, col size: 11

Note: though not necessarily in error, it is normally unusual
to have a number of column address bits exceed 10. It is recommended
to double check the DRAM data sheet to ensure the correct column count and
to set unused column address bits in registers ADDRMAP3 and ADDRMAP4 to 0xF
or else the there will be a miscalculation of the total density

Two chip selects are used
Number of DDR controllers used on the SoC: 1
Density per chip select: 3072MB
Density per controller is: 6144MB
Total density detected on the board is: 6144MB
============================================

MX8M-plus: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @2000Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @200Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @50Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @2000Mhz...
[Process] End of initialization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@2000MHz.......Pass
Verifying DDR frequency point1@200MHz.......Pass
Verifying DDR frequency point2@50MHz.......Pass
[Result] OK

============ Step 3: DDR parameters processing... ============
[Result] Done

Success: DDR Calibration completed!!!
DDR Stress Test Iteration 1
--------------------------------
--Running DDR test on region 1--
--------------------------------

t0.1: data is addr test
...

[simonng]

Hi Igor,

Do you have any update on this case?

Regards,

Simon