Strange resolution on LVDS Display. Too much Width.

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Strange resolution on LVDS Display. Too much Width.

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steffendoster
Contributor IV

Hi,

I successfully created a Devicetree for an i.MX6Q which gave me the ability to start Linux (3.14) and Debian 8 (Jessie) with KDE.

Everything works really fine! OK, but this is not my problem.

After that, I downgraded the Device to an i.MX6S. And this was mostly also successful. With one issue:
The resolution of the display seems somehow wrong and far too wide.

I have a DLC0700JMG-T-4 LVDS-Display with a resolution of 1024x600 at 60Hz. This works perfect with the Quad-Core. But when I change to Solo-Core, the whole Picture is stretched to the width and only about 680 Pixels from the left side of the screen are visible in the Display. See screenshot for further details.

The LDB Devicetree-Part of the SOLO Core is:

/* LVDS Display Bridge */

/* Don't use compatible-string "fsl,imx6q-ldb" on i.MX6Solo. This will NOT work! */

ldb: ldb@020e0008 {

    compatible = "fsl,imx53-ldb";

    #address-cells = <1>;

    #size-cells = <0>;

    clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,

             <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,

             <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,

             <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,

             <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;

    clock-names = "ldb_di0", "ldb_di1",

                  "di0_sel", "di1_sel",

                  "ldb_di0_div_3_5", "ldb_di1_div_3_5",

                  "ldb_di0_div_7", "ldb_di1_div_7",

                  "ldb_di0_div_sel", "ldb_di1_div_sel";

    gpr = <&gpr>;

    status = "okay";

    lvds-channel@0 {

        #address-cells = <1>;

        #size-cells = <0>;

        reg = <0>;

        crtc = "ipu1-di0";

        fsl,data-mapping = "jeida";

        /*fsl,data-mapping = "spwg";*/

        fsl,data-width = <24>;

        primary;

        status = "okay";

        display-timings {

            native-mode = <&timing0>;

            /* Display Timings for TFT-Display DLC0700JMG */

            timing0: dlc0700jmg {

                clock-frequency = <49000000>;

                hactive = <1024>;

                vactive = <600>;

                hfront-porch = <48>;

                hback-porch = <144>;

                hsync-len = <96>;

                hsync-active = <0>;

                vfront-porch = <3>;

                vback-porch = <11>;

                vsync-len = <10>;

                vsync-active = <1>;

            };

        };

        port@0 {

            reg = <0>;

            lvds0_mux_0: endpoint {

                remote-endpoint = <&ipu1_di0_lvds0>;

            };

        };

        port@1 {

            reg = <1>;

            lvds0_mux_1: endpoint {

                remote-endpoint = <&ipu1_di1_lvds0>;

            };

        };

    };

    /* LVDS-Channel 1 leads only to ICT-Pads and doesn't have any function. */

    lvds-channel@1 {

        #address-cells = <1>;

        #size-cells = <0>;

        reg = <1>;

        crtc = "ipu1-di1";

        /*fsl,data-mapping = "jeida";*/

        fsl,data-mapping = "spwg";

        fsl,data-width = <18>;

        status = "disabled";

        port@0 {

            reg = <0>;

            lvds1_mux_0: endpoint {

                remote-endpoint = <&ipu1_di0_lvds1>;

            };

        };

        port@1 {

            reg = <1>;

            lvds1_mux_1: endpoint {

                remote-endpoint = <&ipu1_di1_lvds1>;

            };

        };

    };

};

The LDB Devicetree-Part of the QUAD Core is:

/* LVDS Display Bridge */

/* Don't use compatible-string "fsl,imx6q-ldb" on i.MX6Solo. This will NOT work! */

ldb: ldb@020e0008 {

    compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";

    #address-cells = <1>;

    #size-cells = <0>;

    clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,

             <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,

             <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,

             <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,

             <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,

             <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;

    clock-names = "ldb_di0", "ldb_di1",

                  "di0_sel", "di1_sel",

                  "di2_sel", "di3_sel",

                  "ldb_di0_div_3_5", "ldb_di1_div_3_5",

                  "ldb_di0_div_7", "ldb_di1_div_7",

                  "ldb_di0_div_sel", "ldb_di1_div_sel";

    gpr = <&gpr>;

    status = "okay";

    lvds-channel@0 {

        #address-cells = <1>;

        #size-cells = <0>;

        reg = <0>;

        crtc = "ipu2-di0";

        fsl,data-mapping = "jeida";

        /*fsl,data-mapping = "spwg";*/

        fsl,data-width = <24>;

        primary;

        status = "okay";

        display-timings {

            native-mode = <&timing0>;

            /* Display Timings for TFT-Display DLC0700JMG */

            timing0: dlc0700jmg {

                clock-frequency = <49000000>;

                hactive = <1024>;

                vactive = <600>;

                hfront-porch = <48>;

                hback-porch = <144>;

                hsync-len = <96>;

                hsync-active = <0>;

                vfront-porch = <3>;

                vback-porch = <11>;

                vsync-len = <10>;

                vsync-active = <1>;

            };

        };

        port@0 {

            reg = <0>;

            lvds0_mux_0: endpoint {

                remote-endpoint = <&ipu1_di0_lvds0>;

            };

        };

        port@1 {

            reg = <1>;

            lvds0_mux_1: endpoint {

                remote-endpoint = <&ipu1_di1_lvds0>;

            };

        };

                   

        port@2 {

            reg = <2>;

            lvds0_mux_2: endpoint {

            remote-endpoint = <&ipu2_di0_lvds0>;

            };

        };

        port@3 {

            reg = <3>;

            lvds0_mux_3: endpoint {

            remote-endpoint = <&ipu2_di1_lvds0>;

            };

        };

    };

    /* LVDS-Channel 1 leads only to ICT-Pads and doesn't have any function. */

    lvds-channel@1 {

        #address-cells = <1>;

        #size-cells = <0>;

        reg = <1>;

        crtc = "ipu2-di1";

        /*fsl,data-mapping = "jeida";*/

        fsl,data-mapping = "spwg";

        fsl,data-width = <18>;

        status = "disabled";

        display-timings {

            native-mode = <&timing1>;

            timing1: dlc0700jmg {

                clock-frequency = <51200000>;

                hactive = <1024>;

                vactive = <600>;

                hback-porch = <220>;

                hfront-porch = <40>;

                vback-porch = <7>;

                vfront-porch = <21>;

                hsync-len = <60>;

                vsync-len = <10>;

            };

        };

        port@0 {

            reg = <0>;

            lvds1_mux_0: endpoint {

                remote-endpoint = <&ipu1_di0_lvds1>;

            };

        };

        port@1 {

            reg = <1>;

            lvds1_mux_1: endpoint {

                remote-endpoint = <&ipu1_di1_lvds1>;

            };

        };

                   

        port@2 {

            reg = <2>;

            lvds1_mux_2: endpoint {

            remote-endpoint = <&ipu2_di0_lvds1>;

            };

        };

        port@3 {

            reg = <3>;

            lvds1_mux_3: endpoint {

            remote-endpoint = <&ipu2_di1_lvds1>;

            };

        };

    };

};

Any Idea?

Labels (4)
4 Replies

1,219 Views
steffendoster
Contributor IV

Hello again,

I think I found the answer:

although it's dangerous to play with the display-parameters, I changed the clock-frequency and now I have the correct resolution.

My working display-timings in devicetree is now:

/* Display Timings for TFT-Display DLC0700JMG */

timing0: dlc0700jmg {

    clock-frequency = <69000000>;

    hactive = <1024>;

    vactive = <600>;

    hfront-porch = <48>;

    hback-porch = <144>;

    hsync-len = <96>;

    hsync-active = <0>;

    vfront-porch = <3>;

    vback-porch = <11>;

    vsync-len = <10>;

    vsync-active = <1>;

};

But is it save to use these settings???? Can someone verify this?

1,219 Views
jamesbone
NXP TechSupport
NXP TechSupport

I do not have the same display that you are using but we have change the settings in the Hanstar LVDS  of the SABRE i.MX6 board and it was save to change it.

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1,219 Views
jamesbone
NXP TechSupport
NXP TechSupport

Hello Steffen,

From the image, seems that the LVDS it is failing in X11, have you try to modify the X11.conf  file to change the resolution?  What about the bootargs are this configure according to the resolution that you are expecting?


Have a great day,
Jaime

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1,219 Views
steffendoster
Contributor IV

It can't be a problem with X11.

Reason:

- On startup of the Linux-Kernel the board shows one (Solo) or four (Quad) Tux to show how many Cores are identified by the System. On Quad Core, the Tux looks as fat as ever. But on Solo Core, Tux looks much fater (wider). On Solo it also looks blurry from side to side but not from top to bottom.

- My iMX6Q uses the identical RootFS with the same X11, same KDE, same everything and doesn't stretch the screen.

This is why the error must be somewhere in the Kernel (Devicetree), right?

Thanks for the fast answer.

Steffen

PS: The bootargs for Quad AND Solo are:

console=ttymxc1,115200 root=/dev/mmcblk0p2 rootwait rw video=mxcfb0:dev=ldb,1024x600 at 60,if=RGB24

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