Strange Behavior of Coresight Module of i.MX 6SoloX SABRE Board

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Strange Behavior of Coresight Module of i.MX 6SoloX SABRE Board

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hjkim2
Contributor I

 My team is doing a project that uses PTM of ARM CoreSight Framework. We should get the branch trace from linux system inside the board with ETB. (Not using JTAG)

 We are using Cortex-A9 core only and trying with 4.14.78 linux-imx kernel from github / u-boot, root file system made from Yocto release.

 We could get a trace from the PTM, but it seems that result is abnormal. We followed these procedures described below.

 First, Referring this link - https://community.nxp.com/message/872513?commentID=872513#comment-872513

We edited device tree with the code inside the link. And changed reg address (referring to IMX6SXRM) and clock (to IMX6SX_CLK_AXI / also tested with IMX6SX_CLK_AHB)

 Next, we tried different versions of coresight drivers.

 

First, we tried with old coresight driver that composed of coresight.h, etm.c. Because we edited the code to configure PTM and other components' register, and succeeded to get PTM trace from the other board. After tracing procedure on sample program with PTM, we could get only 5 words output  from ETB. 

ffffffff
00800100
00000000
00000000
00000000

 

We tried to test with various values that we can set on PTM and other components' register, but all results were same.

We also tried with newer CoreSight driver that included in 4.14.78 without any register configuration. Trace in ETB was

21000000

00000180

00000000

00000008

and other fields were 0 in ETB.

 

Question is

1. Is there any other extra configuration to get normal trace? Such as clock that should be enabled or any other fundamental settings?

2. If we did right setting for tracing with PTM, It seems that PTM or ETB is malfunctioning.

 Especially ETB size is different from the size that written in IMX6SXRM. In the reference Manual, ETB's Trace RAM size is 2KB, but ETB's size register says ETB's size is 16KB. That is built- in constant that set from the RTL Design. So It makes me confused.

3. I want to know exact PTM's port size. It's not in the manual. I could know ETM of Cortex M4's Port Size is 8bit, but not PTM.

Please help us. We used almost a month to find out the solution. :smileysad:

I'm looking forward to expertise's sincere advise. Thank you :smileyhappy:

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  

Hope the following helps:

 

 

https://community.nxp.com/message/468279

 

Note, for kernel debugging the following configuration should be provided:

 

Add Kernel debugging

              -> Kernel hacking

                              [*] Compile Kernel with debug info

                            . . .

                              [*] Tracers

                                          [*] Kernel Function Tracer

 

                -> General Setup

                            [*] Profiling Support

 

Remove CAAM/SNVS Security Violation Handler

 

                -> Cryptographic API

                              -> Hardware crypto devices

                                          <> CAAM/SNVS Security Violation Handler


Have a great day,
Yuri

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hjkim2
Contributor I

It seems that this option doesn't work well :smileysad:

We bought a new board 'i.MX 6QuadPlus SABRE Development Board', andhttps://www.nxp.com/support/developer-resources/evaluation-and-development-boards/sabre-development-...

we used exactly same kernel and edited devicetree. We emulated jtag_clk for the errata with memory mapped writing, and PTM worked well.

Sadly, jtag_clk is not the main cause of malfunctioning PTM in i.MX 6SoloX

Is there any other things that we can try for the PTM?

And I want to try Cortex-M4's ETM's functionality too. but it seems there is no DAP register information in IMX6SXRM Manual

Please tell me about the way to control Cortex-M4's ETM or DAP register address for ETM

Thank you :smileyhappy:

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

   I am afraid the i.MX6 QP board cannot be used for the tracing with special bus, since

corresponding pins are used for other functionality. 

    So, using the ETB with JTAG is the only way. 

Regards,

Yuri.

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hjkim2
Contributor I

Yes. We could get PTM trace from ETB within linux-support with i.MX6QP. (just dump etb's data into file)

But we have to make SoloX work.

We confirmed that SoloX's PTM also works when JTAG is connected. After connecting J-Link JTAG emulator, we could get trace in ETB even after disconnecting JTAG.

So it seems that JTAG connection enables something inside Board. We want to enable PTM without JTAG connection. so, we want to know the condition that PTM is enabled. (That condition dependent on signal sequences from JTAG port. if we know that condition, we can make signal with pull-up/down register intentionally.)

Can we get that condition?

Thank you :smileyhappy:

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

 in the following discussion https://community.nxp.com/message/1151194 :

according to ARM "the trace is read out at low speed, typically using a JTAG ...".

It is not clear if other ways are available for ETB read; we do not have experience here,

sorry.

 

Regards,

Yuri.

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