I'm trying to boot M4 core from Linux running on A53 cores on I.MX8MQ evaluation kit.
While searching for exact steps required to boot M4 core I came across AN 5317 titled
"Loading Code on Cortex-M4 from Linux for
the i.MX 6SoloX and i.MX 7Dual/7Solo
Wanted to ask where can I find equivalent document for I.MX8MQ?
Hi Rita Wang,
Thank you for your quick reply.
I've already read the link you have shared but I'm asking code level steps to boot M4 core from Linux. Kindly see section 3.2 of AN 5317 that I've also referenced in my query.
3.2. Detailed procedure
In order to reload the code on the Cortex-M4 core using the Cortex-A7 processor on i.MX 7Dual/7Solo users have to follow the steps below:
1. Issue a software platform reset by setting up SW_M4P_RST (Bit 2) in the SRC_M4RCR
(SRC_M4RCR) register. Issuing a platform reset, resets the Cortex-M4 cores and associated memories. The address of SRC_M4RCR register is 0x3039_000C for i.MX 7Dual/7Solo SoC.
2. Load the code for the Cortex-M4 processor into the TCM_L memory. For this application, we
assume that the Cortex-M4 code is compiled to execute from TCM_L memory. From Table 1,
the TCM_L address from the Cortex-A7 side is 0x007F_8000, therefore users need to program
the binary file generated by the FreeRTOS to that address.
3. Once the file has been loaded, the next step is to setup the Stack and PC pointer in the
OCRAM_S memory, because after reset the processor uses the OCRAM_S start address
(0x0018_0000) as the first instruction. For this implementation, the stack value is the first four
bytes found in the binary file generated for the Cortex-M4 processor using FreeRTOS source.
The PC value is also four bytes long and is located at an offset of 0x4 in the binary file. This PC value is written to the OCRAM_S base address plus four which for this platform is
(0x0018_0004). Table 2 further clarifies the Stack and PC addresses.
4. Once the startup address in the OCRAM_S have been adjusted according to the binary file and the file has been loaded into the memory. The next step is to set the ENABLE_M4 (Bit 3) in the
SRC_M4RCR (SRC_M4RCR) register. Since the bootaux already booted a primary image,
this bit should be 1. Performing a platform reset using SW_M4P_RST (Bit 2) in the
SRC_M4RCR (SRC_M4RCR) register does not clear this bit. The last step is to set the
SW_M4C_RST (Bit 1) in the SRC_M4RCR (SRC_M4RCR) register which will boot the
new code on the Cortex-M4 processor.
As AN 5317 only covers i.MX 6SoloX and i.MX 7Dual/7Solo processors I'm looking for equivalent steps for I.MX8MQ processor.