Some feedback to i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 3, 07/2015

[martin_maurer]

Hello,

[Info/pages updated from rev. 1 to rev. 3, 07/2015]

here some feedback to "i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 3, 07/2015".

1) According to page 507 PLL5 seem to go from 650MHz to 1300MHz.

But page 796 list 630MHz as one and only frequency. Cut&Paste error from PLL4?

2) Is 132MHz as default frequency correct for IPU2_DI0_CLK_ROOT? All other IPUx_DIy_CLK_ROOT show 180MHz...

(Page 808)

3) Page 859 shows "Selector for ldb_di1 clock multiplexer" even for "11–9 ldb_di0_clk_sel".

4) Page 1625: "Input video Vertical active pixel region width. Number of Vertical active lines [0...4095]."

But field has only 8 bits, so max 255?

5) Page 2892: IPU_DP_COM_CONF_SYNC Register address 0x1F40000. Correct? Same for SRM entries

and all following entries up to following page and register IPU_DP_CSC_ASYNC1_1?

(to page 2893 and 2894)

6) Page 3251: Bit 18: "Post-Processing Task color conversion RGB-->YUV enable. This bit enables YUV-->RGB."

Must be "RGB-->YUV" at end of sentence?

Best regards,

Martin

[b36401]

The points 1,2,3,6 you noted seem to be typos.

As for page 1625 (and 1622 as well) please note that actually there are HDMI_FC_INVACTIV0+HDMI_FC_INVACTIV1 pair 8bit registers that provides whole 13bit value.

Have a great day,

Victor

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[martin_maurer]

Hello Victor,

two new things:

1) Just found another small typo: Search for "resister" (occures multiple times, in titles and even later in the text), in my opinion shall be "register".

2) I think a clarification is needed for TEMPMON:

"62.3.1 Tempsensor Control Register 0 (TEMPMON_TEMPSENSE0n)"

-> There is a "n" inside the register name.

"Address: 20C_8000h base + 180h offset + (4d × i), where i=0d to 3d"

-> Address calculation shows "i" goes from 0 to 3.

=> Do we have more than 1 temperature sensor? One for each core?

But OCOTP_ANA1 is only available 1 times, so common for all temperature sensors?

Any updates on the other topics?

Best regards,

Martin

[martin_maurer]

As for page 1625 (and 1622 as well) please note that actually there are HDMI_FC_INVACTIV0+HDMI_FC_INVACTIV1 pair 8bit registers that provides whole 13bit value.

Perhaps the "other" register can be added as in description of register?