We're having some trouble with a custom i.MX6Q board (based on sabreSD reference). It appears that our DDR3 is close to timing margins. I'd like to slow the DDR3 clock rate down to 396MHz. I tried plugging that value into the DDR3 programming spreadsheet and replacing the values in flash_header.S with the updated spreadsheet values. However, when u-boot comes up, its still showing 528MHz for the ddr clock. I also noticed that mx6q pll2 is set to 528MHz. Is there something else I need to do, like change pll2 somehow?
Solved! Go to Solution.
I finally did get past this problem. Ultimately what I was trying to do was calibrate the DDR3 RAM against the 1.2 GHz Quad core part. I ended up having to go through this interesting procedure with the calibration tool.
First, I put the memory parameters into the DDR3 spreadsheet provided by Freescale.
I used the calibration values from this spreadsheet to seed the DDR3 calibration tool. I then ran the tool and got new calibration values. I took the output of this tool and fed the values back into the inputs of a second run of the tool. I did this several times until I discovered that output values were converging. I then took the converged output values and used them in the u-boot code for calibration and voila, the 4 GB of RAM has worked like a charm since. I hope this helps you.
Wow, what a great piece of code.
One question I have is this. If you change the clk settings don't you also have to also change the calibration parameters associated with the DDR3? If you set the clk to 400 MHz and don't change the calibrations, I would not expect things to work very well.