Single Channel LVDS Display with 1920x1080@60Hz

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Single Channel LVDS Display with 1920x1080@60Hz

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schulerstephan
Contributor II


Hello Community,

I want to use a LVDS display with a resolution of 1920x1080 Pixel @60Hz (Dotclock = 148.5 MHz). The display has only a single LVDS Channel with 4 differntial data lines.

I think the limitation is the serializer clock of the LDB which must not be higher than 595 MHz. When I calculate the clock for my display (148.5 MHz Dotclock * 7 Databit = 1039.5 MHz Serializer Clock) this will not work.

Is this up to this point correct?

The solution now is to use the SPLIT mode. But then I have to use both LVDS channels of the i.MX6. One for the ODD data and one for the EVEN data. I have then a SerialzerClock of 519.75MHz, which is lower than the 595 MHz. But than I need an other display that supports the two LVDS channels.

Is this up to this point correct?

The last question is now: Where can I find the information which LVDS channel is responsible for the ODD data and which one for the EVEN data?

Thanks in advance,

Stephan

1 Solution
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alfred_liu
NXP Employee
NXP Employee

Hi, Stephan

1, yes, your caculation is exactly correct, signle LVDS cannot reach 1920*1080/60Hz, we need two LVDS port to support this.

2, I believe the ODD data and EVEN data are configured in our i.mx side, you can refer to our BSP reference code to get it.

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10 Replies
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sebastiannowack
Contributor I

Hallo Stephan

I had similar problemes with the same display (I guess).

I build an android with the sabrelite BSP and changed my parameters

     described in:  https://community.freescale.com/docs/DOC-93617

After I set a frequency lower than 148.5 M pixel / s, I got a running system with a flickering screen. ( pixclock approx. 9000 )

Later I changed an entry kernel_imx/arch/arck/mach-mx6/ckolck.c in function int __init mx6_clocks_init(. . .)

     clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M);

to:

     clk_set_parent(&ldb_di0_clk, &pll5_video_main_clk);

To exclude a conflict while initialising I switched off some entrys in init.rc:

I found, that android boots without the console:

#service console /system/bin/sh

#    class core

#    console

#    user root

#    group root

The system didn't flicker any more, but it became so instable, that a mouse movement turned the screen to black for a second.

I am new in building android, so I don't know if that means, you can reach higher values, than described in the imx6q-specs.

So I think you're right, and the 595 MHz is the maximum for single channel lvds.  I was irritated  by some other entries in the datasheets of imx and/or sabrelite.

Thanks,

Sebastian

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alfred_liu
NXP Employee
NXP Employee


Hi,Stephan

the attached LCD is a dual LVDS panel, Maybe you can refer to.

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EgleTeam
Contributor V

Stephan,

please pay attention on page 482 of the reference manual (dual-quad): max. frequency for single channel is 85mhz, so it is not possible to achieve 1920x1080@60.

Regards,

Manuel.

3,954 Views
schulerstephan
Contributor II

Hi Manuel,

thanks! The 85MHz Pixelclock are exactly the maximum serializer clock (85MHz * 7 Bit = 595 MHz). That will confirm my calculation! :smileyhappy:

Regards,

Stephan

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alfred_liu
NXP Employee
NXP Employee

Hi, Stephan

1, yes, your caculation is exactly correct, signle LVDS cannot reach 1920*1080/60Hz, we need two LVDS port to support this.

2, I believe the ODD data and EVEN data are configured in our i.mx side, you can refer to our BSP reference code to get it.

3,954 Views
schulerstephan
Contributor II

Hi Weisong Liu,

thanks for you answer!

I have to check the configuration for odd an even with my colleagues. Maybe I will come back later to this point.

To solve the hardware point I think there are two possible solutions:

1. We have to change the display to a dual channel LVDS type

2. We will use the parallel RGB interface which supports a pixelclock up to 264 MHz (single port) and then we have to use a external LVDS seralizer that support a higher bitrate.

Are there any other thinks to regard relating to the parallel RGB interface with a FullHD resolution? For lower resolutions this works fine for us!

Regards,

Stephan

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alfred_liu
NXP Employee
NXP Employee

Hi, Stephan

you really undersatand our RM document deeply.

there is indeed two way to meet your requirement.

while I recommend you use two LVDS port to do this.

because I don't think 148.5MHz dotclock is a good thing for us( jitter, PCB layout, EMI.......).

3,954 Views
schulerstephan
Contributor II

Hi Weisong Liu,

i am completely with you!

Furthermore I couldn't find a RGB to LVDS bridge which supports the 148 MHz.

Many Thanks for your help!

Regards,

Stephan

3,954 Views
EgleTeam
Contributor V

TI has few transmitters for >150Mhz. Unfortunately those work at 1.8V: almost sure due the arguments that said Weisong.

Thanks,

Manuel.

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EgleTeam
Contributor V

Stephan,

In our modules we only did the fanout of one channel. Sounds interesting to use a LVDS serializer from RGB.

Thanks!

Manuel.

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