Simultaneous work of A9 and M4 in IMX6SoloX

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Simultaneous work of A9 and M4 in IMX6SoloX

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aureliengrange
Contributor II

Hello everybody,

Before starting a new design with an IMX6SoloX, I would like to know how to exchange around 10Ko between M4 and A9.

I want to use the M4 for real-time operation (1ms) and the A9 to do computation and HMI (Web Server, LCD, …).

I have planned to put Linux on an SD card and then running it on the DDR and using a quad SPI Flash for running FreeRTOS.

Does someone has test communication between A9 (Linux) and M4 (MQX or FreeRTOS) (for more than few octets)?

I will use precise location in DDR to exchange data (as a shared memory). But what will happen if the M4 try to write data in DDR in the same time that Linux is running in?

  • Does it create latency or does writing operation will be canceled?
  • Is there a hardware way to do this or should I use interrupts to prevent the other core that data exchange is in progress? I have not found information (or not understand) about RDC and precise state in case of collision occurs.

I also have a question about the simultaneous use of two different peripheral simultaneously.

I see in the reference manual that SPBA allow only one master to access the required peripheral.

     But what’s happening for the other (does it create an interrupt, a wait state,…)?

Thanks a lot for your help.

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Yuri
NXP Employee
NXP Employee

Hello,

1.

  You may use multi-core communication support for RPMsg. Please

refer to  RPMsg PingPong or String Demo of the recent BSPs for

i.MX6 SoloX.

http://www.nxp.com/webapp/Download?colCode=L3.14.52_1.1.0_LINUX_DOCS&Parent_nodeId=13376994810717061...

http://www.nxp.com/webapp/Download?colCode=L3.14.52_1.1.0_MX6QDLSOLO&Parent_nodeId=13376994810717061...

https://www.nxp.com/webapp/Download?colCode=FREERTOS_MX6SX_1.0.0_WIN&appType=license&location=null&f...

https://www.nxp.com/webapp/Download?colCode=FREERTOS_MX6SX_1.0.0_LINUX&appType=license&location=null...

2.

  Strictly speaking, although it is possible to use shared memory for efficient

interprocessor communication, simultaneous accesses are not supported in

hardware.   The Messaging Unit may be used for accessing shared memory directly

and avoiding collisions :

The Processor A or Processor B can access shared memory resources of the

SoC directly. However, to avoid simultaneous access to shared memory by both

cores, the MU provides a method (to prevent simultaneous access) using

interrupts and transmit-receive registers for both processors.

  Also, Cortex-A (ARMv7-A) and Cortex-M (ARMv7-M) support exclusive

access instructions (LDREX/STREX), but the SEM4 should be involved here :

the first core to attempt to access the memory should flag the memory as locked

out in using the SEMA4, perform the LDREX/STREX and then clear the SEMA4, the

other core should check the SEMA4 before attempting to access the memory.


Have a great day,
Yuri

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almarto
Contributor IV

Hi Juri,

We do have a similar issue with A5(linux) and M4(FreeRTOS) in MAC57D5xx.

Could yo please provide any example of MCC operation?

Thanks in advance.

BR

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Yuri
NXP Employee
NXP Employee
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1,607 Views
Yuri
NXP Employee
NXP Employee

Hello,

1.

  You may use multi-core communication support for RPMsg. Please

refer to  RPMsg PingPong or String Demo of the recent BSPs for

i.MX6 SoloX.

http://www.nxp.com/webapp/Download?colCode=L3.14.52_1.1.0_LINUX_DOCS&Parent_nodeId=13376994810717061...

http://www.nxp.com/webapp/Download?colCode=L3.14.52_1.1.0_MX6QDLSOLO&Parent_nodeId=13376994810717061...

https://www.nxp.com/webapp/Download?colCode=FREERTOS_MX6SX_1.0.0_WIN&appType=license&location=null&f...

https://www.nxp.com/webapp/Download?colCode=FREERTOS_MX6SX_1.0.0_LINUX&appType=license&location=null...

2.

  Strictly speaking, although it is possible to use shared memory for efficient

interprocessor communication, simultaneous accesses are not supported in

hardware.   The Messaging Unit may be used for accessing shared memory directly

and avoiding collisions :

The Processor A or Processor B can access shared memory resources of the

SoC directly. However, to avoid simultaneous access to shared memory by both

cores, the MU provides a method (to prevent simultaneous access) using

interrupts and transmit-receive registers for both processors.

  Also, Cortex-A (ARMv7-A) and Cortex-M (ARMv7-M) support exclusive

access instructions (LDREX/STREX), but the SEM4 should be involved here :

the first core to attempt to access the memory should flag the memory as locked

out in using the SEMA4, perform the LDREX/STREX and then clear the SEMA4, the

other core should check the SEMA4 before attempting to access the memory.


Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

1,606 Views
niranjanbc
Contributor IV

Hi Yuri

I am looking for MCC library in FreeRtos

can you please provide the link for the same.

currently we have used MCC between A9(linux) and M4(MQX)

but we are planning to replace MQX with FreeRtos, but i dont find example code or MCC library for FreeRtos.

 

thanks

Niranjan

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Yuri
NXP Employee
NXP Employee

Hello,

  please refer to the following 

https://community.nxp.com/thread/451000 

Regards,

Yuri.

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aureliengrange
Contributor II

Hello Yuri,

Thanks for your answer.

So to summarize the best way if I want to share more than 496o is to use MU to prevent the other core that the resource is in use and read data when the lock is released.

I had taken a look to these two command (LDREX/STREX) this morning just before reading your comment :-).

It is very interesting that you taught about it. I haven’t understand how to integrate a global monitor in the shared memory (in parallel NOR  memory via EIM for example):

During RPMSG exchanges what is the state when the A9 is waiting reply from M4 (does it wait, does the scheduler preempt other task,…)?

Do you know if there is latency if the two cores are writings data (a lot) in two different peripherals (as there is only one AXI bus)?

      Or does the RDC bus can connect separately on two different bus peripheral that are not shared?

Thanks for your help

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Yuri
NXP Employee
NXP Employee

Hello,

Strictly speaking there is no global lock monitor in the system to support
LDREX / STREX.  The Cortex-A9 has local lock monitor, so the STREX / LDREX
can be used to implement lock/free code on the A9 CPU only.  But the Cortex-M4
CPU does not support the global monitor/AXI signals needed to have multi-core
lock/free code.  This is the reason for the SEMA4 module.  SEMA4 just implements
hardware-enforced semaphores.

Regards,

Yuri.

1,606 Views
aureliengrange
Contributor II

Thanks

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