Sharing GPIOs of same bank between Cortex-M and Cortex-A

[Bhavin-Sharma]

Hi Everyone,I am using few GPIOs of bank GPIO1 within the Cortex-M7 application while a few gpios from same bank are accessed from Linux driver i.e. Cortex-A. Below are my observations:

    1. If I insert the driver module (linux driver) before starting the Cortex-M application, both the           cores are able to update their respective gpio states properly.

   2. If the application for Cortex-M is started before inserting the linux driver module, the                    application of cortex-M is not able to write the gpio states, and the gpio states stay high.

Do I need to disable the entire GPIO bank from the dts for Cortex-A, in order to access it form cortex-M? Or is there any other way around?
Thanks,

Bhavin

IMX8MPLUS 

[anicolle]

Hello again, 

In your post, you mentioned that you were able to control GPIOs from the same bank while both the M7 and A55 cores were running. If you don’t mind, I would really appreciate it if you could share a bit more about your setup and how you made it work. Your experience might help me identify what I’m missing.

How did you allow both OSes to access the shared GPIO bank?
In my case, the M33 core runs the System Manager. I’ve configured it to grant read, write, and full API access to all cores. However, once Linux boots, it seems to modify something in the TRDC, and Zephyr can no longer access the GPIO as expected.

Thank you very much for your time and consideration.
Wishing you a great day.

[Bhavin-Sharma]

Hey there,

In my application cortex-A only updates the GPIO states in the intialization stage, prior to that it does not update from cortex-A, hence cortex-M is able to drive the gpio states continuously. But once some new configurations are set I need to initialize again due to which the cortex-A has to drive the GPIOs again and this prohibits cortex-M from updating GPIOs.

However, I have found one document which specifically describes this scenario. Find the link of the document and refer to section 2.4. This document is specific to I.MX8M Plus, but I think same would be applicable to your SoC too.

Regards,

Bhavin

[anicolle]

Thanks a lot !

[anicolle]

Hello,

I’m experiencing a similar issue. Could you please update your post if you find any solution? I’ve posted my own question here:

: https://community.nxp.com/t5/i-MX-Processors/IMX95-Linux-and-Zephyr-sharing-GPIO3-ressource/m-p/2085...
Thank you !

[Bhavin-Sharma]

Will surely update.