Shared PVCC_XXX_CAP pins on iMX7D

[chris_f]

What is the role of the PVCC_XXX_CAP pins? Specifically, what happens with PVCC_XXX_CAP pins that are shared between modules with different NVCC supply connections? e.g. PVCC_SAI_SD_CAP when NVCC_SAI=3.3V and NVCC_SDX=1.8V? or PVCC_EPDC_LCD_CAP when NVCC_EPDC=1.8V and NVCC_LCD=N.C.?

[art]

In fact, these PVCC supplies do not provide the actual I/O voltages, but just supply the internal level shifters of I/O pads with equal voltages, that's why they can be internally shorted together and share external decoupling capacitors.

Also, please note that it is not possible to power the I/O supply voltages "partially", i.e. all of the NVCC_xxx power rails must be powered with their respective supply voltages for normal operation, so, your case of "NVCC_EPDC=1.8V and NVCC_LCD=N.C." is non-functional.

Have a great day,
Artur

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[chris_f]

Thanks for the reply.

Can you clarify what you mean by "it is not possible to power the I/O supply voltages "partially""?

IMX7DCEC page 30 says:

"The NVCC_XXX can be off in RUN mode / Low Power mode if all the pads in that IO bank is not used
in the application, the NVCC_XXX supply could be tied to GND."

Is the datasheet wrong or is it that all NVCC_xxx rails with a common PVCC supply must be powered?

[art]

Oh, sorry, my last statement was about i.MX6 series processors, not i.MX7 ones. And, yes, the NVCC_xxx rails of the i.MX7 processors can remain unpowered even in the Run mode if all of the I/O pads in the corresponding power bank are not used. And this does not affect the use of the PVCC_xxx_CAP pads.