Shape of single ended DDR3 clock

[tkl]

Hi,

I have received the prototypes of a custom board I designed with an i.MX6ULL and DDR3L RAM. I use one 16-Bit RAM IC. I have finished calibrating the RAM and everything seems to run fine so far (tests in a climatic chamber are still to come). Now I measured the clock signal of the RAM to see if the termination is ok. In the picture I measured CLK_N to GND with an active probe. I am wondering why there is a change in the amplitude of the signal.

Everything seems to be within the allowed limits but I want to understand why the amplitude is changing like it is. Since this is the clock my understanding is that only the CPU is driving this signal, so I didn't expect to see something like this. In the design I use 100Ohm between the clk lines as termination. I do not use VTT termination. I measured this while running stress test tool v2.8.

[igorpadykov]

Hi Torben

amplitude change can be caused by variations NVCC_DRAM power supply.

General power and decoupling recommendations can be found in

Hardware Development Guide for the i.MX 6ULL Applications Processor
https://www.nxp.com/docs/en/user-guide/IMX6ULLHDG.pdf

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[tkl]

Hi Igor

thanks for your answer. I followed the guide in the design but I will measure the voltage to be sure. I can see similar amplitude changes on the imx6ullevk board.

Update:

I measured NVCC_DRAM and there are no variations.