Set asrc input clock to SPDIF_RX_CLK on IMX6

[manuel_soledge]

Hi,

I am working on an audio application using an i.MX6ULL and I need to use the hardware ASRC of the processor with the S/PDIF RX clock on the asrc pair input.

The problem I have I that even after the S/PDIF dpll is locked I can't read the rate of the spdif_rx_clk so the pair configuration fails to calculate the input divisor.

In the reference manual I read that after the spdif dpll is locked the received rate is directly generated to spdif_rx_clk. Is that right or are there registers to configure to make it go through to the asrc controller?

Thank you,

Manuel BA

[igorpadykov · Accepted solution]

Hi Manuel

S/PDIF RX clock is described in sect.50.4.1.8 

i.MX 6ULL Applications Processor Reference Manual

some spdif tests which may be useful:

doc\mxc_spdif_test\test - imx-test - i.MX Driver Test Application Software 

doc\mxc_asrc_test\test - imx-test - i.MX Driver Test Application Software 

Best regards
igor
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[manuel_soledge]

Hi,

Thank you for your answer, I have been able to recover the RX clock in the asrc module.
I also have opened another question about the asrc clock sources.

Manuel