Sample schematics for connecting two LPDDR2 with i.MX7D

cancel
Showing results for 
Search instead for 
Did you mean: 

Sample schematics for connecting two LPDDR2 with i.MX7D

Jump to solution
363 Views
ko-hey
Senior Contributor II

Hi all

Does someone have experience for connecting two LPDDR2 ?

My customer plan to connect two LPDDR2 with i.MX7.

When 2 GB of memory capacity is used, we plan to use 2 LPDDR2 x32 1GB RAM in parallel.
It is assumed to be used with switching by CS [1: 0].

Unfortunately, we can't find out a reference schematics.

Does someone have a reference schematic ?

If yes, please share it.

Ko-hey

Labels (3)
0 Kudos
1 Solution
94 Views
Yuri
NXP TechSupport
NXP TechSupport

Hello,

  As for one LPDDR device - really we have here single package, but several devices.

Control DRAM signals DRAM_DQMx, DRAM_SDQSx, address and data lines  DRAM_ADDRESSx,
DRAM_SDBAx, DRAM_DATAx, clock DRAM_SDCLK0 are common for all DRAM devices.

DRAM_CS0,  DRAM_SDCKE0, DRAM_ODT0 select and control  one device (CS0), 

DRAM_CS1,  DRAM_SDCKE1, DRAM_ODT1 - the second. 

Regards,

Yuri.

View solution in original post

0 Kudos
4 Replies
94 Views
Yuri
NXP TechSupport
NXP TechSupport

Hello,

You may  look at WaRP7|NXP 

The following about LPDDR3 and LPDDR2 differences may be useful:

< https://www.micron.com/~/media/documents/products/technical-note/dram/lpddr3/tn_5202_lpddr3_design_l... >


Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
94 Views
ko-hey
Senior Contributor II

Hi YuriMuhin_ng

I checked a schematic but it looks only one LPDDR device…

Ko-hey

0 Kudos
95 Views
Yuri
NXP TechSupport
NXP TechSupport

Hello,

  As for one LPDDR device - really we have here single package, but several devices.

Control DRAM signals DRAM_DQMx, DRAM_SDQSx, address and data lines  DRAM_ADDRESSx,
DRAM_SDBAx, DRAM_DATAx, clock DRAM_SDCLK0 are common for all DRAM devices.

DRAM_CS0,  DRAM_SDCKE0, DRAM_ODT0 select and control  one device (CS0), 

DRAM_CS1,  DRAM_SDCKE1, DRAM_ODT1 - the second. 

Regards,

Yuri.

View solution in original post

0 Kudos
94 Views
ko-hey
Senior Contributor II

Hi Yuri Muhin

Thank you for reply.

I understand.

Ko-hey

0 Kudos