SSI's TXC from external and TXFS from internal, is it possible?

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SSI's TXC from external and TXFS from internal, is it possible?

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robyf
Contributor IV

Hi All,

I'm playing with a custom board having the SSI connected to a SLIC in TDM mode. The SSI has TXC (PCLK) coming from an external oscillator running at 2.048MHz while TXFS (FSYNC) is set to be generated from internal. The SSI documentation is not really clear in case, so wondering to know if it is possible to generate FSYNC with this particular configuration: SSI set in I2S normal mode, synchronous transfers, network mode, TXC taken from external oscillator. Doesn't anyone can give an answer?

I've a similar custom board feeding both TXC and TXFS from internal but this seems not generating stable FSYNC over the time, and the SLIC goes in fault after 2 o 3 days of continuous running due to instable FSYNCs.

Thanks in advance,

Roberto Fichera.

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igorpadykov
NXP Employee
NXP Employee

Hi Roberto

 

if SRCK should be outputted (TXDIR=1)

this is not possible.

~igor

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abhijeet_ghodga
Contributor III

Hi Roberto,

In my case, the FSync pulse out of sync within few minutes of running SLIC IC.

I have used ALSA driver to read and write 8-bit Mu Law data with SLIC.

I am able to write the data but I am unable to read it. Parameters are PCLK=512kHz and FSync=8kHz.

Any driver to read data accurately, with masking and proper synchronisation with SSI will be helpful.

The stock ALSA driver, and fsl-soc-pcm driver go out of sync immediately.

Best,

Abhijeet

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robyf
Contributor IV

Hi Igor,

Yes! I've tried to follow what the iMX6SX reference manual is reporting but without success. FSYNC still not generated by the SoC. The relevant part reported in RM doc (62.8.4 SSI Clocking) is:

In master and synchronous mode, the unused port SRCK is used as network clock (oversampling clock) enabled by the SCR register bit 15, SYS_CLK_EN. This network clock is an oversampling clock of the frame sync clock (STFS). In this mode, the word length (WL), Prescaler Range (PSR), Prescaler Modulus (PM) and Frame rate (DC) selects the ratio of network clock to sampling clock STFS. In case of I2S mode, the network clock (oversampling clock) can be made available on this port if the SYS_CLK_EN bit is set.

However, accordingly with Figure 62-22 network clock on SRCK can be activated only when both TXDIR and SYS_CLK_EN are set. But if TXDIR is set I cannot get STCK from external oscillator because SSI is now generating it from internal. I've also changed the way how audmux is routing FYSNC, internal port is SSI1 and external is SSI6

int audmux_config(unsigned int master, unsigned int slave, bool external)
{
unsigned int ptcr, pdcr;

ptcr = IMX_AUDMUX_V2_PTCR_SYN /* Synchronous mode */
        | IMX_AUDMUX_V2_PTCR_TCSEL(slave); /* transmit clock select from external port */

pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(slave);
audmux_v2_configure_port(master, ptcr, pdcr); /* configure internal port */

ptcr = IMX_AUDMUX_V2_PTCR_SYN
        | IMX_AUDMUX_V2_PTCR_TFSDIR /* Transmit Frame Sync from Internal */
        | IMX_AUDMUX_V2_PTCR_TFSEL(master); /* from master port */

pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(master);
audmux_v2_configure_port(slave, ptcr, pdcr); /* configure external port */
return 0;
}

and SSI1 is set with this relevant setup:

scr = CCSR_SSI_SCR_I2S_MODE_NORMAL |
         CCSR_SSI_SCR_SYN | /* Synchronous mode */
         CCSR_SSI_SCR_NET; /* Network mode to enable TDM */

stcr = CCSR_SSI_STCR_TXBIT0 | /* LSB Aligned */
           CCSR_SSI_STCR_TFDIR | /* Transmit Frame Direction Internal - generated internally */
           CCSR_SSI_STCR_TFEN0 | /* Enable TX FIFO0 */
           CCSR_SSI_STCR_TSCKP; /* Transmit Clock Polarity - Data Clocked out on falling edge */

Cheers,

Roberto Fichera.

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purvi_billore
Contributor I

Hello Roberto,

Could you please share your machine driver and platform driver files of SLIC; I am also working on SLIC and want to compare your driver files with my files.

Thanks and Regards,

Purvi

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igorpadykov
NXP Employee
NXP Employee

Hi Roberto

I believe you are right: drawing on the scene

SRCK changes answer to opposite.

Best regards
igor

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robyf
Contributor IV

Hi Igor,

is it an answer or should I wait a final confirmation?

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igorpadykov
NXP Employee
NXP Employee

Hi Roberto

 

if SRCK should be outputted (TXDIR=1)

this is not possible.

~igor

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robyf
Contributor IV

Hi Igor,

Ok! Thanks!

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igorpadykov
NXP Employee
NXP Employee

Hi Roberto

bit and frame clocks are contrlolled independently with

TXDIR,TFDIR, please check Figure 62-22, 62-23

i.MX6SX Reference Manual, so it may work

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf

Note there are some clock restrictions described in sect.62.8.4.2.

Best regards
igor
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