SRAM using EIM on i.mx6sx

weilunhuang · ‎08-07-2023

I hope you are doing well.

We connect a static RAM (cy62167ev30) using the EIM interface in a custom i.mx6sx board. We are trying to set an MTD filesystem in that SRAM. The Linux kernel version is 5.15.17, and in DTS we have.

pinctrl_weim_cs0: weim-cs0-grp {

fsl,pins = <

MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0b0b1 /* sram CS0 */

>;

};

pinctrl_weim_sram: weim-sram-grp {

fsl,pins = <

MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x0b0b1

MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0b0b1

MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0b0b1

MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x0b0b1

MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0b0b1

MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0b0b1

MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0b0b1

MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0

MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0

MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0

MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0

MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0

MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0

MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0

MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0

MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0

MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0

MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0

MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0

MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0

MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0

MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0

MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0

MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x0b0b1

MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0b0b1

MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0b0b1

MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0b0b1

MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x0b0b1

MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0b0b1

MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0b0b1

MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0b0b1

MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x0b0b1

MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x0b0b1

MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x0b0b1

MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x0b0b1

MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x0b0b1

MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0b0b1

MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0b0b1

MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0b0b1

MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x0b0b1

MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0b0b1

MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0b0b1

MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0b0b1

>;

};

&weim {

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0>;

#address-cells = <2>;

#size-cells = <1>;

status = "okay";

/* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */

ranges = <0 0 0x50000000 0x02000000

1 0 0x52000000 0x02000000

2 0 0x54000000 0x02000000

3 0 0x56000000 0x02000000>;

fsl,weim-cs-gpr = <&gpr>;

/* SRAM on CS0 */

sram_rtc@0,0 {

#address-cells = <1>;

#size-cells = <1>;

bank-width = <2>;

compatible = "cypress,cy62167ev30", "mtd-ram";

reg = <0x0 0x0000 0x00200000>;

/* EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1, EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 */

fsl,weim-cs-timing = <0x00010001 0x00000000 0x03000000

0x00000008 0x03000000 0x00000000>;

sram-filesys@0 {

reg = <0x0 0x1ff000>;

};

sram-raw@1ff000 {

reg = <0x1ff000 0x1000>;

};

i.MX6 Configuration Register Settings

EIM bus registers :

EIM_CS0GCR1 00010001

EIM_CS0GCR2 00000000

EIM_CS0RCR1 03000000

EIM_CS0RCR2 00000008

EIM_CS0WCR1 03000000

EIM_CS0WCR2 00000000

When I attempted to write "0x 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11" to the SRAM, two extra bytes "0xFFFF" were unexpectedly added at the beginning of the address I was trying to write.

00000000 FF FF 11 11 11 11 11 11 11 11 11 11 11 11 11 11 ................

00000010 11 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

00000030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

00000040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

00000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

Could you please suggest what might be wrong with my configuration?

Thanks for your help.

Rita_Wang · ‎08-07-2023

You do not use the DDR in your design? For the SRAM to the EIM of the i.MX6SX section design, could you share this section circuit ?

weilunhuang · ‎08-07-2023

We do use DDR in our design, the SRAM is for our customer's application.

Please see the attached for reference. Thank you for your help.

SRAM using EIM on i.mx6sx

SRAM using EIM on i.mx6sx

i.MX6SoloX