Hello,
I am writing my own SPI driver. I need to use ECSPI 5 on iMX6QP. I am following the instructions in the datasheet regarding the initialization of the the ECSPI 5 module. I am configuring the registers directly using /dev/mem and mmap funtion.
The problem is, I am not able to measure any CLK singal on the pad SD1_CLK.
The instructions in the Datasheet are:
1. Clear the EN bit in ECSPI_CONREG to reset the block.
2. Enable the clocks for ECSPI within the CCM.
3. Configure the Control Register and then set the EN bit in the ECSPI_CONREG to
put ECSPI out of reset.
4. Configure corresponding IOMUX for ECSPI external signals.
5. Configure registers of ECSPI properly according to the specifications of the external
I do everything listed above. I suspect, that there is a problem with the CCM. There is a register CCM Clock Gating Register 1 (CCM_CCGR1) where I enable the CG4 ecspi5 clocks (ecspi5_clk_enable). But I am not sure about other registers in CCM.
According to the Table 18-3. System Clocks, Gating, and Override, this field should enable signals ipg_clk and ipg_clk_per.
But there is also CCM Clock Output Source Register (CCM_CCOSR), there is field CLKO2_SEL where I set ecspi_clk_root and also CLKO2_EN which I enable.
IO-MUX setting:
IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT is set to 0: SD1_CLK_ALT1
(with ALT2 — Select signal XTALOSC_OSC32K_32K_OUT I can see clk signal, so the PAD is ok)
IOMUXC_SW_MUX_CTL_PAD_SD1_CLK is set to 001: ALT1 — Select signal ECSPI5_SCLK.
Control Register (ECSPI5_CONREG) is in the end set to: 0x000458F1
CHANNEL_SELECT: 01b
PRE_DIVIDER: 101b (6x)
POST_DIVIDER: 1000b (256x)
CHANNEL_MODE: 1111b
I also tried to modify the devicetree:
ecspi@02018000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x2018000 0x4000>;
interrupts = <0x0 0x23 0x4>;
clocks = <0x2 0x74 0x2 0x74>;
clock-names = "ipg", "per";
dmas = <0xe 0xb 0x8 0x1 0xe 0xc 0x8 0x2>;
dma-names = "rx", "tx";
status = "ok";
spidev@0 {
compatible = "spidev";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
I am able to see then the /dev/spidev4.0 . This sets the ECSPI5_CONREG to 0x0070E3F1, which is a valid setting, but an spi example test program, which uses dev/spidev fails and I am neither able to see clk signal on the associated PAD. (I modify the IOMUX by mmap in this case as well).
Please help.
