SPDIF Rx Clock (SPDIF_SR_CLK) pulse rate

[yoshida_satoru]

I'm planning to use the SPDIF from the i.MX RT 1060.
The reference manual (IMXRT1060RM.pdf) has the following explanation in 40.3.1.7:

> After DPLL has locked, the pulses are generated, and the average pulse rate is 128 x the sampling frequency.(For a 44.1 Khz input sampling frequency, the average pulse rate = 128 x 44.1 Khz.)

When the SPDIF input is 44100Hz, 88200Hz, or 176400Hz, I want to get an output of 22,579,200Hz.
When the SPDIF input is 48000Hz, 96000Hz, or 19200Hz, I want to get an output of 22,579,200Hz.
To achieve this I want to change the multiplier to x128.

Is it possible to change the x128 magnification?

[mayliu1 · Accepted solution]

Hi @yoshida_satoru 

Thank you for your interest in the NXP MIMXRT product, I would  like to provide service for you.

As you mentioned in IMXRT1060RM reference manual, It describe "After DPLL has locked, the pulses are generated, and the average pulse rate is 128 x the sampling frequency."

I don't think It is possible to change the x128 magnification.

The SPDIF interface of  i.MX RT1060 chip is designed as a fixed multiplier of x128, and user can not be configured to use a different multiplier.

Wish it helps you.
If you still have question about it, please kindly let me know.

BR

mayliu