SMPTE274 and SMPTE296 on i.mx6

[djb33]

Hello all,

    I am currently looking to output via the parallel interface of the i.mx6 the standards SMPTE274 and SMPTE296.

According to the reference manual (page 2699 of IMX6DQRM.pdf) the processor supports SMPTE274 and SMPTE296 in the parallel interface:

"37.1.2.1.2.2 Display Interface

The display interface is very flexible and supports a wide variety of devices from major

manufacturers. The following interface types are provided (in each of the two display

ports)

• Parallel video interface (for synchronous access) - up to 24-bit data bus.

  • Compatible with MIPI-DPI standard .

  • Control protocol - follows Sharp HR and generic TFT definitions

  • Supports BT.656 (8-bit) and BT.1120 (16-bit) protocols

  • Supports HDTV standards SMPTE274 (1080i/p) and SMPTE296 (720p)"

Also found in IMX6DQAE.pdf on page 99 it explains the ports, signals, and balls which both SMPTE standards can be output on.

I am looking to output the 20-bit format YCrCb.

The last column on the right side of Table 69 shows 20-bit YCrCb and the associated Port Names ('EDM Conn' refers to Wandboard):

Port Name                     EDM Conn Name           20-bit YCrCb        Ball

IPU1_DISP0_DAT00 -      DISP0_DAT0                     C[0]                P24 

IPU1_DISP0_DAT01 -      DISP0_DAT1                     C[1]                P22

IPU1_DISP0_DAT02 -      DISP0_DAT2                     C[2]                P23

IPU1_DISP0_DAT03 -      DISP0_DAT3                     C[3]                P21

IPU1_DISP0_DAT04 -      DISP0_DAT4                     C[4]                P20

IPU1_DISP0_DAT05 -      DISP0_DAT5                     C[5]                R25

IPU1_DISP0_DAT06 -      DISP0_DAT6                     C[6]                R23

IPU1_DISP0_DAT07 -      DISP0_DAT7                     C[7]                R24

IPU1_DISP0_DAT08 -      DISP0_DAT8                     C[8]                R22

IPU1_DISP0_DAT09 -      DISP0_DAT9                     C[9]                T25

IPU1_DISP0_DAT10 -      DISP0_DAT10                   Y[0]                R21

IPU1_DISP0_DAT11 -      DISP0_DAT11                   Y[1]                T23

IPU1_DISP0_DAT12 -      DISP0_DAT12                   Y[2]                T24

IPU1_DISP0_DAT13 -      DISP0_DAT13                   Y[3]                R20

IPU1_DISP0_DAT14 -      DISP0_DAT14                   Y[4]                U25

IPU1_DISP0_DAT15 -      DISP0_DAT15                   Y[5]                T22

IPU1_DISP0_DAT16 -      DISP0_DAT16                   Y[6]                T21 

IPU1_DISP0_DAT17 -      DISP0_DAT17                   Y[7]                U24

IPU1_DISP0_DAT18 -      DISP0_DAT18                   Y[8]                V25

IPU1_DISP0_DAT19 -      DISP0_DAT19                   Y[9]                U23

IPU1_DI0_DISP_CLK -     DI0_DISP_CLK                PixCLK             N19

IPU1_DI0_PIN02 -           DI0_PIN2                         HSYNC             N25

IPU1_DI0_PIN03 -           DI0_PIN3                         VSYNC             N20

The problem that arises is I have no clue how to setup the processor to do such. Could someone please point me in the right direction to register maps or the likes?

This help is greatly appreciated.

My current setup is a Wandboard with i.mx6 Quad running Yocto 1.5

Thanks for your help.

K

[Yuri]

When configuring display output pins, the following should be taken into account.

1.

General scheme is shown on Figure 37-32 (Mapping scheme) of the i.MX6DQRM.

2.

From Table 37-25 (DC template's fields description) :

«The MAPPING field holds a pointer to a register holding 3 fields: MAPPING_PNTR_BYTE0_X,

MAPPING_PNTR_BYTE1_X, MAPPING_PNTR_BYTE2_X. This pointers point to sets of OFFSET and

MASK parameters that define the mapping scheme. MAPPING =0 means that mapping is disabled.»

3.

Section 37.4.7.5.1 (Bus Mapping Unit) describes the mapping feature in more details.

On the Figure 37-32 (Mapping scheme), microcode field MAPPING = 2.

That is, register IPUx_DC_MAP_CONF_1 should be used for configuring; please refer to section 37.5.336

[DC Mapping Configuration Register 1 (IPUx_DC_MAP_CONF_1)] of the Reference Manual.

As an example let we set :

MAPPING_PNTR_BYTE2_2 = 2

MAPPING_PNTR_BYTE1_2 = 1

MAPPING_PNTR_BYTE0_2 = 0

then

IPUx_DC_MAP_CONF_15 register should be set as following :

(section 37.5.350 DC Mapping Configuration Register 15 (IPUx_DC_MAP_CONF_15))

MD_OFFSET_1 = 0x0D ; MD_MASK_1 = 0xFC

MD_OFFSET_0 = 0x05 ; MD_MASK_0 = 0xFC

IPUx_DC_MAP_CONF_16 :

MD_OFFSET_2 = 0x16 ; MD_MASK_2 = 0xFC

4.
Please refer to Chapter 18 (Configuring the IPU Driver) of "iMX6_Firmware_Guide.pdf" in the Platform SDK.

https://www.freescale.com/webapp/Download?colCode=i.MX6_PLATFORM_SDK&location=null

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&fpsp=1&tab=Design_Tools_Tab

[djb33]

This is good information but seems extremely low level...is there a u-boot parameter that could facilitate this?

Has anyone tried using the parallel interface for SMTPE274 and SMPTE296?

Thanks,

K

[Yuri]

Freescale Linux kernel does not implement it.

Please look at Table 6 (Kernel Boot Parameters) in "i.MX_6Dual6Quad_SABRE-SD_Linux_Release_Notes.pdf" :

TVOUT: YUV444

VGA: GBR24

HDMI&DVI: RGB24

CLAA WVGA LCD: RGB565

[joshkurland]

Hi Yuri,

I am also interested in using the SMPTE standards with my project.  Is Freescale ever planning on releasing a patch to support these formats, like what they did with BT.656 and BT.1120 (https://community.freescale.com/docs/DOC-94019)?  Or are developers who want this format on their own?

Thank you,

Josh Kurland

[Yuri]

I am afraid - developers should provide needed formats themselves.