SJA1105QELY interface with i.MX6

[Kirisave]

Hi All,

We are using Ethernet switch from NXP and the part# is SJA1105QELY. The block diagram is as shown below.

Request your inputs on the below queries:

• We would like to know if SJA1105QEL has internal voltage level translator to convert the PHY side MII signal (3.3V) to Host side MII signal (1.8V)?
• We have connected 25MHz crystal to PHY and the clock output of the PHY is feed into Ethernet Switch (SJA1105QELY), hope this will be fine??  

[Sabeur]

Hi @Kirisave,

1. Each switch MAC can operate at different supply voltages, as highlighted in the text.
   Please do not confuse VDDIO_HOST with the VDDIO_MII of the MII host port
2. In the MII interface mode, both TX_CLK and RX_CLK are provided by the PHY, so in principle and at a high level, the fact that the PHY provides a 25 MHz clock is what is expected.
   Each SJA1105 port can be configured as an MII MAC or MII PHY, and in the MII MAC role it expects the clock to be present, while in the MII PHY role it drives the clock.

Best regards,

Sabeur