SGTL5000 master clock from SoC

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SGTL5000 master clock from SoC

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kunal_003
Contributor III

Hi All,

 

We are usign SGTL5000 codec in our i.MX8MPlus design. The SAI3_MCLK pad is used as the master clock source for codec. We are not able to generated the master clock, as per the SGTL5000 datasheet only after having master clock we would be able to communicate over I2C. Temporary we tried with external crystal and we are able to play with mic and speaker. However, we need to provide master clock from processor.

 

Below is the device tree node relevant to codec:

codec: sgtl5000@2a {
    compatible = "fsl,sgtl5000";
    reg = <0x2a>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sgtl5000>;
    VDDA-supply = <&reg_audio_3p3v>;
    VDDIO-supply = <&reg_audio_1p8v>;
    assigned-clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
    assigned-clock-rates = <12288000>;
    clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
    clock-names = "mclk";
    status = "okay";
};

pinctrl_sgtl5000: sgtlgrp {
    fsl,pins = <
        MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
    >;
};

 

&sai3 {
    #sound-dai-cells = <0>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sai3>;
    assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
    assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
    assigned-clock-rates = <12288000>;
    clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
    <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
    <&clk IMX8MP_CLK_DUMMY>;
    clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
    status = "okay";
};

 

Anything I am missing in device tree w.r.t clock? Please help me generating master clock with the help of device tree.

 

Thanks in advance!

Regards,

Kunal

40 Replies

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Kunal

 

one can look at sgtl5000 example on

https://github.com/Freescale/linux-fslc/blob/5.9.x%2Bfslc/arch/arm64/boot/dts/freescale/imx8mq-libre...

 

Best regards
igor

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kunal_003
Contributor III

Hi @igorpadykov ,

 

Thank you for the pointer. I did some modifications based on the example you provided, still I am not seeing any master clock generated on that pin. Below is the modified device tree node and also I have attached the clock summary tree from sysfs.

 

sound {
compatible = "simple-audio-card";
simple-audio-card,name = "sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker Ext",
"Line", "Line In Jack";
simple-audio-card,routing =
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"Speaker Ext", "LINE_OUT";

simple-audio-card,cpu {
sound-dai = <&sai3>;
};

simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
frame-master;
bitclock-master;
};
};

 

/* codec */
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
#sound-dai-cells = <0>;
reg = <0x0a>;
status = "okay";
};

&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
status = "okay";
};

 

Am I still missing anything?

 

Regards,

Kunal

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kunal_003
Contributor III

Hi @igorpadykov , @weidong_sun,

 

From clock summary it seems the clock is enabled and active. However, I am still not able to detect codec. From below snap of codec driver, I checked that mclk in codec is set properly and "clk_prepare_enable" in not giving any error while generating mclk. I printed the mclk and it is 12288000, which I believe is proper. Any guess on why it is not generating the clock?

sgtl-codec-driver.png

Regards,

Kunal

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xiaocong_fu
NXP Employee
NXP Employee

Hi @kunal_003 

Are you measuring the SAI3 MCLK pin with an oscilloscope?

BTW, the SAI3 configuration is already in arch/arm64/boot/dts/freescale/imx8mp-evk.dts, you can just copy from it.

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kunal_003
Contributor III

Hi @xiaocong_fu ,

 

Yes, I am measuring in oscilloscope, as well as the SGTL5000 codec driver is giving error "Error reading chip id -6". With external crystal everything works fine. Also, initially I tried with the SAI3 configuration from "imx8mp-evk.dts", however, with this as well it is not working.

Also, one point that I wanted to understand, in case of "imx8mp-evk.dts", wm8960 is used and the SAI3 will generate the mclk whenever we play or record something. While in case of SGTL5000, it is codec driver which generates the mclk. Is this understanding about wm8960 and SGTL5000, correct?

Also, do we need to add the property "fsl,sai-mclk-direction-output" in sai3 node? As per the "SAI MCLK Control Register" from Reference manual, bit 30 indicates that mclk pin will act as input or output. However, I am confused if this is used only when SAI driver is generating clock and not if codec driver is generating the mclk. By the way, I tried adding this property as well, but unable to generate mclk.

 

Regards,

Kunal

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xiaocong_fu
NXP Employee
NXP Employee

@kunal_003 

Please also have a try with the modification:

    sound {
        compatible = "simple-audio-card";
        simple-audio-card,name = "sgtl5000";
        simple-audio-card,format = "i2s";
        simple-audio-card,widgets =
            "Microphone", "Microphone Jack",
            "Headphone", "Headphone Jack",
            "Speaker", "Speaker Ext",
            "Line", "Line In Jack";
        simple-audio-card,routing =
            "MIC_IN", "Microphone Jack",
            "Microphone Jack", "Mic Bias",
            "LINE_IN", "Line In Jack",
            "Headphone Jack", "HP_OUT",
            "Speaker Ext", "LINE_OUT";

        simple-audio-card,cpu {
            sound-dai = <&sai3>;
        };

        simple-audio-card,codec {
            sound-dai = <&sgtl5000>;
            clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>;
            frame-master;
            bitclock-master;
        };
    };


    sgtl5000: audio-codec@a {
        compatible = "fsl,sgtl5000";
        clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>;
        #sound-dai-cells = <0>;
        reg = <0x0a>;
        VDDD-supply = <&reg_1v8_p>;
        VDDIO-supply = <&reg_3v3_p>;
        VDDA-supply = <&reg_3v3_p>;
    };

&sai3 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sai3>;
    assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
    assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
    assigned-clock-rates = <12288000>;
    clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
         <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
         <&clk IMX8MP_CLK_DUMMY>;
    clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
    fsl,sai-mclk-direction-output;
    status = "okay";
};
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xiaocong_fu
NXP Employee
NXP Employee

Hi @kunal_003 

Here is the normal flow in fsl_sai driver: 

When start capture/playback, sai driver is called, in fsl_sai_hw_params, mclk will be enabled; when stop capture/playback, in fsl_sai_hw_free, mclk will be disabled. In your case, did you call the sai driver?When you tried with external crystal, I assume the external crystal will provide mclk to codec constantly. You can try the attached patch, it will keep mclk in "on" state after calling the sai driver for the first time.

>>Also, one point that I wanted to understand, in case of "imx8mp-evk.dts", wm8960 is used and the SAI3 will generate the mclk whenever we play or record something. While in case of SGTL5000, it is codec driver which generates the mclk. Is this understanding about wm8960 and SGTL5000, correct?

 In both cases, SAI3 will generate the mclk. Why would you think in case of SGTL5000, codec driver will generate the mclk?

Yes "fsl,sai-mclk-direction-output"  should be set, when SAI driver is generating clock, the mclk is out for SAI, and is in for codec.

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kunal_003
Contributor III

Hi @xiaocong_fu 

  1. I tried with the above nodes suggested by you. It seems the difference is renaming of "audiomix_clk" with "audio_blk_ctrl" and similarly "IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1" with "IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1". I believe the renamed macro are used in latest BSP. We are using "imx_5.4.70_2.3.0" Kernel branch. So, I used the macros that were originally used in this source. From this also I am unable to detect the codec and SGTL5000 driver gives below error:

    [ 5.344481] sgtl5000_i2c_probe-1617 clk_rate:12288000
    [ 5.356386] sgtl5000 1-000a: Error reading chip id -6

  2.  I tried the patch as well but no codec detection happened.
  3. The reason I thought SGTL5000 is generating mclk, is because from below snapshot, probe of codec driver is enabling mclk and giving 8 pulse delay and then reading chip ID. 

sgtl-codec-driver.png

 

Note: This time I have not measured in oscilloscope and taking decision based in codec detection only. Also, I verified the mclk pin as a GPIO and it toggles as expected. I am stuck with this mclk only and have tried with various approaches. Any approach from h/w or f/w perspective is appreciated.

 

Thanks in advance!

Regards,

Kunal

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xiaocong_fu
NXP Employee
NXP Employee

Hi @kunal_003 

I checked the usage of SGTL5000 in other boards, and start to understand why it's not working in your case. We can compare some cases.

1. With external crystal, mclk is provided to codec constantly.

2. In other boards where SGTL5000 is used, there is always a dedicated sys_mclk for the codec, rather than using sai mclk. For example, you can check arch/arm/boot/dts/imx6ul-pico-pi.dts or arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts

    sys_mclk: clock-mclk {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <24576000>;
    };
            codec: sgtl5000@a {
                #sound-dai-cells = <0>;
                compatible = "fsl,sgtl5000";
                reg = <0xa>;
                VDDA-supply = <&reg_3p3v>;
                VDDIO-supply = <&reg_3p3v>;
                clocks = <&sys_mclk>;
            };

3. The problem of using sai mclk is explained previously: When start capture/playback, sai driver is called, in fsl_sai_hw_params, mclk will be enabled; when stop capture/playback, in fsl_sai_hw_free, mclk will be disabled. That's to say, sai mclk cannot be kept constant. With my patch "test_mclk_on.patch", sai mclk can be set "on" after calling sai driver once. But I think it's not enough, need to figure out how to enable mclk in probe stage. 

Below is an updated dts:

    sound {
        compatible = "simple-audio-card";
        simple-audio-card,name = "sgtl5000";
        simple-audio-card,format = "i2s";
        simple-audio-card,widgets =
            "Microphone", "Microphone Jack",
            "Headphone", "Headphone Jack",
            "Speaker", "Speaker Ext",
            "Line", "Line In Jack";
        simple-audio-card,routing =
            "MIC_IN", "Microphone Jack",
            "Microphone Jack", "Mic Bias",
            "LINE_IN", "Line In Jack",
            "Headphone Jack", "HP_OUT",
            "Speaker Ext", "LINE_OUT";

        simple-audio-card,cpu {
            sound-dai = <&sai3>;
        };

        simple-audio-card,codec {
            sound-dai = <&sgtl5000>;
            frame-master;
            bitclock-master;
        };
    };

    sys_mclk: clock-sys-mclk {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <12288000>;

    sgtl5000: audio-codec@a {
        compatible = "fsl,sgtl5000";
        #sound-dai-cells = <0>;
        reg = <0x0a>;
        VDDD-supply = <&reg_1v8_p>;
        VDDIO-supply = <&reg_3v3_p>;
        VDDA-supply = <&reg_3v3_p>;
		clocks = <&sys_mclk>;
    };

&sai3 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sai3>;
    assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
    assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
    assigned-clock-rates = <12288000>;
    clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
         <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
         <&clk IMX8MP_CLK_DUMMY>;
    clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
    fsl,sai-mclk-direction-output;
    status = "okay";
};

 

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kunal_003
Contributor III

Hi @xiaocong_fu,

 

My understanding on your comparisions:

  1. Agree
  2. I believe dedicated "sys_mclk" means there would be some pin in SoC that will provide fix constant clock. As we defince the sys_mclk with some rate, but physical pins like gpio should be there. Right?
  3. I agree that the patch wont be able to keep the clock constant. However, regarding "need to figure out how to enable mclk in probe stage. "==> As per this code snippet
    codec driver is enabling mclk for 8 pulses and then reading the CHIP ID from sensor. 
  4. I tried with the updated dts and it is not working. I am not sure how sys_mclk will generate clock on some physical pins. Can you please explain me with that?

Regards,

Kunal

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kunal_003
Contributor III

Hi @xiaocong_fu,

 

Did you got chance to look at my last response? I saw the schematic of PICO-PI, they are using external crystal as an mclk to sgtl5000. Can you please confirm this?

 

Also, in codec driver mclk rate is properly achieved still it is not showing any signal over oscilloscope. Do I need to enable any other parent clock for the same? Is there any way to read CCM registers, as memtool is giving bus error?

 

Regards,

Kunal

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xiaocong_fu
NXP Employee
NXP Employee

Hi @kunal_003 

> I saw the schematic of PICO-PI, they are using external crystal as an mclk to sgtl5000. Can you please confirm this?

Yes. I also consulted an expert with experience of sgtl5000, and the response was that sgtl5000 was using external crystal. Is using external crystal possible in your platform?

In parallel, I'm working on the sai driver code, trying to figure out how to enable mclk in system bootup. As I said the previous patch only generates mclk after calling sai driver, eg after using aplay -Dhw:x,y xxx.wav, mclk can be up.

 

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kunal_003
Contributor III

Hi @xiaocong_fu ,

 

We already designed with MCLK from SAI pin. So, it seems it won't be feasible to use external crystal.

 

Also, why we are finding an option for enabling mclk at boot time in SAI driver? Can't we enable the mclk from codec driver? There is already snippet in sgtl5000.c. It is enabling the clock and waiting for 8 pulse. Can you please guide me on why are we focusing on enabling mclk from sai driver only?

 

What specifically SAI driver does and not the codec driver? I think we can add that particular portion from SAI to codec driver, if it is enabling some parents clock and pll. As far as I saw, it is not enabling pll for i.MX8MP in SAI driver. So there should not be anything extra in SAI driver.

 

Please share your thoughts. Thank you in advance!

 

Regards,

Kunal

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xiaocong_fu
NXP Employee
NXP Employee

Hi @kunal_003 

sgtl5000 cannot generate mclk, it can only receive mclk from either external crystal of sai mclk, that's why we're focusing on the sai driver.

I haven't finished the modification yet, but found one example https://github.com/engicam-stable/meta-engicam-mx8/blob/master/recipes-kernel/linux/linux-imx/0005-a...

Please refer to it first.

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kunal_003
Contributor III

Hi @xiaocong_fu,

 

I tried taking reference of enigcam device tree and modified the device tree and codec driver. However, results are same. If you have the engicam schematic then can you please share the same? I need to look whether the mclk is output of SAI or not. Below is the modified device tree based on reference taken from meta-engicam:

 

        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <0>;

                reg_3v3_avdd_sgtl: reg_3v3_avdd_regulator {
                        compatible = "regulator-fixed";
                        regulator-name = "3v3_avdd_sgtl";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        always-on;
                };

                reg_3v3_sgtl: reg_3v3_sgtl_regulator {
                        compatible = "regulator-fixed";
                        regulator-name = "3v3_sgtl";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
                        always-on;
                };

                reg_1v8_sgtl: reg_1v8_sgtl_regulator {
                        compatible = "regulator-fixed";
                        regulator-name = "1v8_sgtl";
                        regulator-min-microvolt = <1800000>;
                        regulator-max-microvolt = <1800000>;
                        always-on;
                };
        };

        sound {
                compatible = "simple-audio-card";
                simple-audio-card,name = "imx8mm-sgtl5000";
                simple-audio-card,format = "i2s";
                simple-audio-card,bitclock-master = <&dailink_master>;
                simple-audio-card,frame-master = <&dailink_master>;
                /*simple-audio-card,mclk-fs = <1>;*/
                simple-audio-card,cpu {
                        sound-dai = <&sai3>;
                };

                dailink_master: simple-audio-card,codec {
                        sound-dai = <&sgtl5000>;
                        clocks = <&clk IMX8MP_CLK_SAI3>;
                };
        };

        sgtl5000: codec@a {
                compatible = "fsl,sgtl5000";
                status = "okay";
                #sound-dai-cells = <0>;
                reg = <0x0a>;
                clocks = <&clk IMX8MP_CLK_SAI3>;
                clock-names = "mclk";
                //assigned-clock-rates = <12288000>;
                assigned-clock-rates = <49152000>;
                VDDA-supply = <&reg_3v3_avdd_sgtl>;
                VDDIO-supply = <&reg_3v3_sgtl>;
                VDDD-supply = <&reg_1v8_sgtl>;
        };
&sai3 {
    #sound-dai-cells = <0>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sai3>;
    assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
    assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
    //assigned-clock-rates = <12288000>;
    assigned-clock-rates = <49152000>;
    clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
         <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
         <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>,
                <&clk IMX8MP_AUDIO_PLL2_OUT>;
    clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
    fsl,sai-mclk-direction-output;
    status = "okay";
};

 

Also, below are the registers of SAI3 read using sysfs.

cat /sys/kernel/debug/regmap/30c30000.sai/registers 
000: XXXXXXXX
004: XXXXXXXX
008: XXXXXXXX
00c: 00000000
010: 00000000
014: 00000000
018: 00000000
01c: 00000000
020: 00000000
024: 00000000
028: 00000000
02c: 00000000
030: 00000000
034: 00000000
038: 00000000
03c: 00000000
040: XXXXXXXX
044: XXXXXXXX
048: XXXXXXXX
04c: XXXXXXXX
050: XXXXXXXX
054: XXXXXXXX
058: XXXXXXXX
05c: XXXXXXXX
060: 00000000
064: 00000000
068: 00000000
06c: 00000000
070: XXXXXXXX
074: XXXXXXXX
078: XXXXXXXX
07c: XXXXXXXX
080: 00000000
084: 00000000
088: XXXXXXXX
08c: 00000000
090: 00000000
094: 00000000
098: 00000000
09c: 00000000
0a0: XXXXXXXX
0a4: XXXXXXXX
0a8: XXXXXXXX
0ac: XXXXXXXX
0b0: XXXXXXXX
0b4: XXXXXXXX
0b8: XXXXXXXX
0bc: XXXXXXXX
0c0: XXXXXXXX
0c4: XXXXXXXX
0c8: XXXXXXXX
0cc: XXXXXXXX
0d0: XXXXXXXX
0d4: XXXXXXXX
0d8: XXXXXXXX
0dc: XXXXXXXX
0e0: 00000000
0e4: 00000000
0e8: 00000000
0ec: 00000000
0f0: XXXXXXXX
0f4: XXXXXXXX
0f8: XXXXXXXX
0fc: XXXXXXXX
100: 40000000 =====> MCLK is configured as output
104: 00000000

If we see the above regmap, mclk is configured as output. I am not sure if anything is else is required to enable/start the mclk pin. Can you please help me with this that what else is required so that I can try some method at my end as well.

 

Regards,

Kunal

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xiaocong_fu
NXP Employee
NXP Employee

Hi @kunal_003 

Please try the attached patch, ignore the printk information.

Note this is a dirty patch with hardcoded parameters. The only purpose is to generate sai mclk at system bootup, to verify sgtl5000 i2c probe.

For the dts, just refer to the attached one.

-----------------------------------------------------------------------------

Just FYI

When you check the register previously, "MCLK is configured as output" is not enough, set as output doesn't mean it is really outputing clk.

You can try the register CLKEN0 0x30e20000, check the bit 8&9. If bit 8&9 are enabled, it means SAI3 mclk is enabled.

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kunal_003
Contributor III

Hi @xiaocong_fu ,

 

Thank you for sharing the patch. I applied this and able to detect the codec over I2C and probe of SGTL5000 is successful. I can see the audio device in "aplay -l".

However, I cannot record and play the audio. I believe it is something with this patch. To verify this, I tried with another setup with same device tree and zImage and providing mclk externally. In this setup I am able to record and play audio files. So I think the patch is causing some issue while recording and playing. Any clue or debug points that I can validate? Can it be something with bit clock and master clock sync? 

 

Regards,

Kunal

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xiaocong_fu
NXP Employee
NXP Employee

Hi @kunal_003 

As you know, I do not have an SGTL5000, I can only test with the default codec wm8960, the playback works correctly. You may also try this on i.MX8MP evk board.

Without the patch, the normal flow is: system bootup -> aplay starts, call sai driver -> trigger starts, transmitter enabled, mclk generated -> aplay stops, call sai driver -> trigger stops, transmitter disabled, mclk stopped.

The patch simply put transmitter enablement and mclk generation at sai probe, so mclk can be active at system bootup. After the first aplay stops, mclk will stop, and the system will behave like a normal case.

One this worth trying is not to disable transmitter, that's to say, comment out FSL_SAI_CSR_TERE reset in sai trigger stop, then mclk can be kept always on. Please check if this can solve your problem and see if any side effect.

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kunal_003
Contributor III

Hi @xiaocong_fu 

 

Master clock is staying on through out the lifecycle. Even after 1st time aplay command the clock is not stopping. Now we can record and play sometimes only and not all the time. We found a dirty sequence which if followed properly then we are able to record and play. We are debugging this further, meanwhile I would like to know if for your case in EVK with this patch is the master clock stopping after first aplay? For me all three clocks are running throughout the system and it seems there is some issue with pm_runtime_suspend/pm_runtime_resume things. 

 

Any inputs are welcome. Thank you.

 

Regards,

Kunal

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xiaocong_fu
NXP Employee
NXP Employee

Hi @kunal_003 

Master clock is staying on through out the lifecycle. Even after 1st time aplay command the clock is not stopping.

Did you add other changes besides the mclk_on_bootup.patch, in sgtl5000.c or imx-sgtl5000.c?

Did you try on the evk board? If not, please try it so we can have a basic alignment. (*for evk, comment out codec-master in dts for sound-wm8960)

From my test on the evk board:

case 1: with only mclk_on_bootup.patch, mclk starts from bootup, and stops after first aplay or arecord. BCLK and LRCLK start when aplay/acreord start, and stop when aplay/acreord stop.

Tried more than 10 times, record and playback are correct through wm8960

case 2: with mclk_on_bootup.patch, do not disable transmitter at trigger stop, mclk will keep always on. BCLK and LRCLK start when aplay/acreord start for first time, and will keep always on. 

Tried more than 10 times, record and playback are correct through wm8960

 

We found a dirty sequence which if followed properly then we are able to record and play

What is the sequence?

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