SGTL5000 VDDIO and LINREG_D_POWERUP.

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SGTL5000 VDDIO and LINREG_D_POWERUP.

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satoshishimoda
Senior Contributor I

Hi community,

I'm using SGTL5000 with i.MX53.

However, some i.MX53 on our custom boards cannot communicate with SGTL5000.

I think this issue is NOT caused by SGTL5000, because 1.8V is supplied from external LDO to VDDD and other I2C slave devices on same bus work correctly.

Then, I want to confirm about SGTL5000.

Please see my questions below.

[Q1]

Please see Table 33 in SGTL5000 datasheet (Rev.6).

I understand LINREG_D_POWERUP initial value is 0x0 and I should set it to 0x0 if 1.8V external power is supplied to VDDD, should I?

But I doubt the initial value because about 1.6V is output from VDDD on the time 3.3V is supplied to VDDIO when power-up.

Is the initial value correct? or should I set it to 0x1 in the case?

[Q2]

Please see Description of ER1 in SGTL5000ER (Rev.2).

It says "The preferred supply sequencing is VDDIO/VDDA(it does not matter which comes first) and then VDDD".

Then, if I supply VDDD before VDDIO or VDDA, what is happen?

Best Regards,

Satoshi Shimoda

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reyes
NXP TechSupport
NXP TechSupport

Hi Satoshi Shimoda,

It seems like the communication problem could be caused by the SGTL5000, as mentioned in the errata ER1 of the errata document “On some very rare combinations of parts and application boards, and on a very small percentage of those rare part/board combinations, sometimes the VDDD internal regulator does not start up after IC power-up” and as a result of this “The most noticeable symptom is that no IC communication/control occurs, and that the I2C bus lines are held in a low state. Power must be cycled to attempt another power-up, and to attempt to regain IC communication. Note that the same applies for SPI communication”.

Please confirm that this is the symptom you are seen in your boards.

If this is your problem, and if a new board development is planned, I would recommend you to follow the steps in the “New Designs” section of the Errata workaround and use an external VDDD, as the external VDDD fix is the only solution that is guaranteed to solve the issue 100% of the time.

Answering to your questions:

[A1] If VDDD is supplied externally, you can leave LINREG_D_POWERUP bit as 0x0 and also LINREG_SIMPLE_POWERUP bit can be cleared (set to 0x0).

[A2] I really don’t know what could happened, but as mentioned this is not critical (it does not matter which comes first), but, if possible, just supply VDDIO/VDDA first and then VDDD.

Regards,

Jose

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reyes
NXP TechSupport
NXP TechSupport

Hi Satoshi Shimoda,

It seems like the communication problem could be caused by the SGTL5000, as mentioned in the errata ER1 of the errata document “On some very rare combinations of parts and application boards, and on a very small percentage of those rare part/board combinations, sometimes the VDDD internal regulator does not start up after IC power-up” and as a result of this “The most noticeable symptom is that no IC communication/control occurs, and that the I2C bus lines are held in a low state. Power must be cycled to attempt another power-up, and to attempt to regain IC communication. Note that the same applies for SPI communication”.

Please confirm that this is the symptom you are seen in your boards.

If this is your problem, and if a new board development is planned, I would recommend you to follow the steps in the “New Designs” section of the Errata workaround and use an external VDDD, as the external VDDD fix is the only solution that is guaranteed to solve the issue 100% of the time.

Answering to your questions:

[A1] If VDDD is supplied externally, you can leave LINREG_D_POWERUP bit as 0x0 and also LINREG_SIMPLE_POWERUP bit can be cleared (set to 0x0).

[A2] I really don’t know what could happened, but as mentioned this is not critical (it does not matter which comes first), but, if possible, just supply VDDIO/VDDA first and then VDDD.

Regards,

Jose

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satoshishimoda
Senior Contributor I

Hi Jose,

Thank you for your reply.

> [A1]

To make sure, could you let me know whether the reset value of LINREG_D_POWERUP on the datasheet (0x0) is correct or wrong also to understand why 1.6V is output from VDDD when 3.3V is supplied to VDDIO?

Best Regards,

Satoshi Shimoda

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reyes
NXP TechSupport
NXP TechSupport

Hi Satoshi Shimoda,

LINREG_D_POWERUP reset value is 0x0, the 1.6V that you are seen in the VDDD is most probably caused by LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits which are by default 0x1. This bit configuration could be causing this output voltage, VDDD linear output regulator will be set by D_PROGRAMMING bits which by default is 0x0 = 1.60V (as mentioned in Table 27 of the datasheet), so, after reset, if VDDD is driven externally, LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits can be cleared (0x0).

Regards,

Jose

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satoshishimoda
Senior Contributor I

Hi Jose,

Thank you for your reply.

And excuse me, I have two additional questions.

[Q3]

According to your reply, SGTL5000 linear regulator output 1.6V immediately after VDDIO/VDDA are supplied and before external VDDD is supplied.

I think power output collision is occurred when VDDD is supplied

Is this no problem?

[Q4]

I want to confirm the meaning of "LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits can be cleared (0x0)."

Which is correct?

(A). "user can clear LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits via I2C after system is powered-up if external VDDD is supplied".

(B). "SGTL5000 clears LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits automatically when external VDDD is detected".

Best Regards,

Satoshi Shimoda

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reyes
NXP TechSupport
NXP TechSupport

Hi Satoshi Shimoda,

Answering to your questions:

[A3] No, this is no problem, as mentioned this is not critical, it does not matter which comes first.

[A4] Option (A) would be the correct one: user can clear LINREG_SIMPLE_POWERUP and STARTUP_POWERUP bits via I2C after system is powered-up if external VDDD is supplied.

Regards

Jose

697 Views
satoshishimoda
Senior Contributor I

Anybody can reply me?

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