SGTL5000 I2S Slave clock configuration

[sumish_ks]

Hello,

I am working on a custom board based on imx6qsabresd where I am using sgtl5000 audio codec as slave . I have configured SSI1 as i2s-master and getting approx. 24 Mhz clock on I2s_sclk pin of codec.

I want to divide this clock and for that I have to configure some registers according to IMX6DQRM manual.

Where should I configure these registers ? I have seen some files in old kernel but these are not present in our freescale 3.14.1.1 linux kernel.

Thanks & Regards,

Sumish

[igorpadykov · Accepted solution]

Hi Sumish

on i.MX6 Sabre SD schematic spf-27392 AUD_MCLK signal is produced from

pad GPIO_0 signal (CCM_CLKO1) GPIO_0_CLKO

Schematics (1)
Design files, including hardware schematics, Gerbers, and OrCAD files

SABRE Platform for Smart Devices|NXP 

Settings for "cko" selection can be found in linux/arch/arm/mach-imx/clk-imx6q.c

linux-2.6-imx.git - Freescale i.MX Linux Tree 

Best regards
igor
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[sumish_ks]

Hi igor,

Thanks for your answer. If I want to modify CCM registers according to our need, can I modify it using .cfg (DCD settings) file or Using memtool directly ?

Regards,

Sumish

[igorpadykov]

Hi Sumish

yes this can be changed with dcd header and memtool.

Best regards
igor

[sumish_ks]

Hi igor,

Thanks for your help.

Regards,

Sumish