SDHC register TUNING_CTR (offset 0xCC)was not found in i.MX8X Reference Manual

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

SDHC register TUNING_CTR (offset 0xCC)was not found in i.MX8X Reference Manual

Jump to solution
924 Views
anguschen
Contributor II

Hi, team

I can not find the description for the SDHC register TUNING_CTR (offset 0xCC) in RM Rev.0(05/2020).

Is this register undocumented or removed?

 

Thank you!

0 Kudos
1 Solution
889 Views
joanxie
NXP TechSupport
NXP TechSupport

refer to the bsp code, it seems

the bit24 is Standard tuning circuit and procedure enable
This field is used to enable standard tuning circuit and procedure.

bit 16-18:TUNING_STEP
The increasing delay cell steps in tuning procedure

bit 7:

Disable command check for standard tuning
Writing 1 to this field disables command check (command CRC, CMD end bit error, and CMD index error
or CMD timeout error) for standard tuning flow after each tuning command is sent

bit0-6:

Tuning start
The start delay cell point when send first CMD19 in tuning procedure

 

View solution in original post

0 Kudos
5 Replies
914 Views
IvanRuiz
NXP Employee
NXP Employee

Hello,

 

Could you please be more specific? Where have you seen this register before, in which document of which products? I cannot find it in the reference manual of the i.MX 8X as you mentioned.

 

BR,

Ivan.

0 Kudos
903 Views
anguschen
Contributor II

Hello, Ivan

Thanks for help. Also I can not find any information about the register in the reference document.

But I found the definition in the BSP source code offered by QNX.

According to the description, this register should be related with the  DLL tunning for eMMC.

I think this register was not publicly documented.

Could you please check this internally?

Thank you!

0 Kudos
890 Views
joanxie
NXP TechSupport
NXP TechSupport

yes, I couldn't find this in the RM either, but maybe you can refer to the bsp, which defines this, and use this as the bsp mentions:

"https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/mmc/host/sdhci-esdhc-imx.c?h=imx_5...

#define ESDHC_TUNING_CTRL		0xcc
#define ESDHC_STD_TUNING_EN		(1 << 24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
#define ESDHC_TUNING_START_TAP_DEFAULT	0x1
#define ESDHC_TUNING_START_TAP_MASK	0x7f
#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE	(1 << 7)
#define ESDHC_TUNING_STEP_MASK		0x00070000
#define ESDHC_TUNING_STEP_SHIFT		16

 

890 Views
joanxie
NXP TechSupport
NXP TechSupport

refer to the bsp code, it seems

the bit24 is Standard tuning circuit and procedure enable
This field is used to enable standard tuning circuit and procedure.

bit 16-18:TUNING_STEP
The increasing delay cell steps in tuning procedure

bit 7:

Disable command check for standard tuning
Writing 1 to this field disables command check (command CRC, CMD end bit error, and CMD index error
or CMD timeout error) for standard tuning flow after each tuning command is sent

bit0-6:

Tuning start
The start delay cell point when send first CMD19 in tuning procedure

 

0 Kudos
864 Views
anguschen
Contributor II

Thanks.

0 Kudos