SD boot issue with i.MX6SL

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

SD boot issue with i.MX6SL

1,264件の閲覧回数
ko-hey
Senior Contributor II

Hi all

My customer have already built a custom board with i.MX6SL and they have a problem with SD boot.

Some of the board fail first boot but it can boot after second time.

They tried following things.

1.It can boot normally when they turn on the power with pressing the reset button

2.It can boot normally when they press the reset button after boot fail

Form the above, they guess it have some problem with reset and clock timing.

So they check the timing of POR_B and XTAL. (Please see a following picture.)

From the pictures, it seems that is has no problem with the timings.

pastedImage_3.png

Then, they checked the SD clock output to confirm the point of where the i.MX is stopped.

As a result, they confirm that the SD clock wasn't output.

pastedImage_4.png

From the results of the investigation, we guess that ERR007927 may cause this issue.

Is there a way to confirm that this errata is caused the issue ?

And do you have any idea to avoid this issue ?

Ko-hey

ラベル(3)
0 件の賞賛
返信
3 返答(返信)

1,103件の閲覧回数
Yuri
NXP Employee
NXP Employee

Hello,

  For such issues, with non stable boot, it makes sense

check power up sequence.

  Also, the erratum ERR007927 may take place, so, please

try workarounds for it.
  Another point for consideration - DDR stress test can help

to find possible memory issues, assuming memory initialization

is the same for the test and customer’s applications.

 

i.MX6/7 DDR Stress Test Tool V2.52

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 件の賞賛
返信

1,103件の閲覧回数
ko-hey
Senior Contributor II

Hi Yuri

Please see the attachment. It shows power up sequence.

Regarding workaround,  they tried 1 to 3 workaround but there are no affect.

Let me confirm about workaround No.4 and No.5.

Those workaround can only do with adding a reset IC. Is my understanding correct ?

Is there any way to do it with SW change ?

Ko-hey

0 件の賞賛
返信

1,103件の閲覧回数
Yuri
NXP Employee
NXP Employee

Hello,

You may try to add a cap to POR - at least just for test.

Regards,

Yuri.

0 件の賞賛
返信