SAI1 with 768K sample rate, will result in FIFO full error

[Chengting]

In reference manual, chapter 1

SAI1 supports to up to 8 I2S/TDM Tx lanes and 8 I2S/TDM Rx lanes at 768kHz/32-
bit

• SDMA mode

 But we use such configuration in M7 part,  refer to the sample code in /evkmimx8mp/driver_examples/sai/sdma_record_playback

Test result: The data not received correctly at all.

• Nonblocking mode(FIFO mode)

Test result: FIFO full error is thrown.

Dear NXP supporters, could you help to give an introduction of how to configure this to avoid the error ?

[Sanket_Parekh]

Hello @Chengting ,

I hope you are doing well.

->Please kindly provide the evk board name that you are using.
->Please kindly share more details on the issue and dmesg logs to debug the issue further.

Thanks & Regards,

Sanket Parekh

[Chengting]

Hi Sanket，

  Quite appreciate your attention.

->Please kindly provide the evk board name that you are using.

   model = "NXP i.MX8MPlus EVK board"
->Please kindly share more details on the issue and dmesg logs to debug the issue further.

Actually we are using M7 core to do receive data from SAI1, the configuration as following:

sample rate = 768 Khz

wordwidth = 32bit

I2s mode , not TDM

Fifo not combined

8 channel ：kSAI_Channel0Mask|kSAI_Channel1Mask|kSAI_Channel2Mask|kSAI_Channel3Mask|kSAI_Channel4Mask|kSAI_Channel6Mask|kSAI_Channel6Mask|kSAI_Channel7Mask

dmesg is in attachment. AS we are using M7 to receive data from SAI1, just dmesg just for reference.

using 8 channel: 

[Sanket_Parekh]

Hello @Chengting ,

I hope you are doing well.

Thanks for the dmesg logs.

->Please make sure the gpio supply voltage for the below symbol is between 3 to 3.6 vol.
NVCC_SAI1_SAI5 (because this power group supplies it to SAI1_RXD0 to RXD7)

->Please make sure that frequency for SAI1_CLK_ROOT is nominal 66 Mhz.

->Please check the pin muxing settings are correct by referring to the table of SAI1 Section 8.1.1.1 Muxing Options.

->Please make sure to check whether the RX_BCLK is well-configured or not in the device tree file because it is the source from where the write FIFO control module passes it to FIFO and then reads the write operation in FIFO Occurs. Receive Bit Clock. The bit clock is an input when I/O is externally generated and an output when internally generated.

Thanks & Regards,

Sanket Parekh

[Chengting]

Hi Sanket ,

   Thank you very much for your concern. 

   I have checked all your point. Now we are trying to test sai in SDMA mode, if new further information, i will report.

    Yours,

                   Chengting.

[Sanket_Parekh]

Hello @Chengting ,

I hope you are doing well.
I'm happy to help.

Please do let me know if you got any updates from your side.

Thanks & Regards,

Sanket Parekh

[Sanket_Parekh]

Hello @Chengting 

I hope you are doing well.

Any updates from your side?

Thanks & Regards,

Sanket Parekh

[Chengting · Accepted solution]

Hi Sanket,

   Thanks for concern this issue.

   Good news is that we resolve this problem.

patch is attached.

by the way, we are using imx8mp_evk.