Hello, @Habib_MS
I've made some testing, changing 63U to 31U :
#define DEMO_SAI3_CLOCK_SOURCE_DIVIDER (31U)
and changing 24bits to 32bits:
#define DEMO_AUDIO_BIT_WIDTH kSAI_WordWidth32bits
makes it possible for the WS to achieve 192kHz without problems.
But when I change it back to 24 bits, WS goes up to 255kHz:
Maybe it has something to do with the word width being distinct to 8/16/32bits?
(i.MX RT1024 Processor Reference Manual, Rev. 1, 02/2021, page 1582)
I've seen this image but I don't understand how should I configure this for 24bits:
(i.MX RT1024 Processor Reference Manual, Rev. 1, 02/2021, page 1581)
Could you please indicate me how can I proceed?
Thanks!
Hello Again @DigitalBrain,
In order to support you better, can you share me the setup that you are currently using to take the signals? Also, in order to try a pinpoint if this macro solves the issue, can you configure the macro with this value and share me the following signals?
#define DEMO_SAI3_CLOCK_SOURCE_DIVIDER (27U)
-MCLK frequency.
-BITCLK frequency.
-WS frequency.
The bit clock divider is calculated in the function called "SAI_TxSetBitClockRate", inside makes this formula:
Where if you set the source clock with a source divider of 31. This bit clock divider will be 2. that causes get more frequency in the WS and the BITCLK. However, if you configure the SAI3_ CLOCK_SOURCE_DIVIDER with 28 the clock divider will be 3.
Also, the next post explains the pictures that you provided me ((i.MX RT1024 Processor Reference Manual, Rev. 1, 02/2021, page 1581))
BR
Habib.
Hello, @Habib_MS
Thanks for getting back to me so quickly
Here's the pinout for the SAI3 module
Configuration: 24bits, 192kHz and #define DEMO_SAI3_CLOCK_SOURCE_DIVIDER (27U)
Results:
-MCLK frequency: 28.11 MHz
-BITCLK frequency: 7.01 MHz
-WS frequency: 146.29 kHz
Hello, @Habib_MS
Indeed, the PCM4104 isn't compatible with that MCLK frequency.
I've achieved the next frequencies but still, not getting a clear sine wave at the output.
This is the configuration:
* AUDIO PLL setting: Frequency = Fref * (DIV_SELECT + NUM / DENOM)
* = 24 * (30 + 72/100)
* = 737.28 MHz
*
* = 737.28 MHz / 2 = 368.64 MHz
Then:
/* Select Audio/Video PLL (737.28 MHz) as sai3 clock source */
#define DEMO_SAI3_CLOCK_SOURCE_SELECT (2U)
/* Clock pre divider for sai3 clock source */
#define DEMO_SAI3_CLOCK_SOURCE_PRE_DIVIDER (0U)
/* Clock divider for sai3 clock source */
#define DEMO_SAI3_CLOCK_SOURCE_DIVIDER (9U)
/* Get frequency of sai3 clock */
#define DEMO_SAI_CLK_FREQ \
(CLOCK_GetFreq(kCLOCK_AudioPllClk) / (DEMO_SAI3_CLOCK_SOURCE_DIVIDER + 1U) / \
(DEMO_SAI3_CLOCK_SOURCE_PRE_DIVIDER + 1U))
So now it is divided by 10 and it goes down to 36.864 MHz
The frequency for BCLK:
bitClockFreq = sampleRate * bitWidth * channelNumbers;
bitClockFreq = 192,000 Hz * 24bits * 2 Channels
bitClockFreq = 9,216,000 Hz
Finally, the frequency of LRCLK succesfully gets to:
192kHz
I'm writing to the registers of PCM4104 so its configuration is as follows:
Sampling Mode: Quad Rate
BCK sampling edge= Rising edge
LRCK Polarity: Normal
Audio Format = 0x00 -> 24-bit left justified (default)
without any luck because the output doesn't sound as the example
Thank you,
DigitalBrainer
Hello, @Habib_MS
Also, I tried scoping Data output from I2S expecting to see the hexadecimal values from music.h file and I found that the values are transmitted but not on the same order as the const uint8_t music[] __ALIGN_END states.
For example, analyzing some random bytes I expected to read
0x75, 0x8E, 0xC8, 0x89, 0xC8, 0x89, 0xFD, 0x85, 0xFD
but on the oscilloscope I got:
0xC8, 0x8E, 0x75, 0x89, 0xC8, 0x89, 0xFD, 0x85, 0xFD
as if they were flipped because some reason I don't get:
Also, could you please explain why MUSIC_LEN is defined as 48000 in the music.h file from the SDK example?
#define MUSIC_LEN (48000)
I suspect this might be causing no sound output due some format error as the example manages 16bits at 16kHz , not 24bits at 192kHz as I'm trying.
Thanks for your support!
