Reset timing in i.MX25

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Reset timing in i.MX25

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yintaoyu
Contributor I

Is the Reset_b signal on i.MX25 level-sensitive or edge-sensitive?

I am currently working on a prototype board with i.MX258, and found that the processor keeps running when Reset_b input is asserted low. Untile Reset_b returns high, the processor restarts.

It seems it's a positive edge-triggered singal, only the rising edge leads to a reset event. But it's not clearly stated in the manual, so I want to make sure is it the expected behaviour?

What's the reset timing like?

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art
NXP TechSupport
NXP TechSupport

Yes, you are right. The RESET_B input of the i.MX25 processor is edge-sensitive. The reset logic operates as follows: first, it detects a rising edge of the RESET_B signal, then it qualifies that RESET_B remains high during 4 CKIL cycles, and after that the cold reset occurs.


Have a great day,
Artur

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68 Views
art
NXP TechSupport
NXP TechSupport

Yes, you are right. The RESET_B input of the i.MX25 processor is edge-sensitive. The reset logic operates as follows: first, it detects a rising edge of the RESET_B signal, then it qualifies that RESET_B remains high during 4 CKIL cycles, and after that the cold reset occurs.


Have a great day,
Artur

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post