Reset of SNVS_LP on some boards but not others

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Reset of SNVS_LP on some boards but not others

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meadowalex
Contributor I

In our IMX6SX based boards, we are currently experience an occasional (on some boards but not others) loss of content of SNVS_LP registers when we are doing a WDOG reset (with POR). It does not seem to be related to the VDD_VSNVS_IN power source: there are no voltage drops there.

1. Is anyone aware of the possible sources of lp_por signal? It's not very well documented in the Reference Manuals.

2. Does anyone know if the BOOTROM is handling any violations in its default config ?

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meadowalex
Contributor I

Hi Weidong,

We have been measuring the voltage of VSNVS_3V0 during the resets that cause the loss of SNVS_LP data and using 2 different Test Points and an Oscilloscope with 1 ms step and there were no voltage drops. It was stable at ~2.96 V.

That is why, having relatively high confidence in the stability of VSNVS_3V0 that we measured during the problematic resets, and in the software boot loader which we are debugging early in it's execution, I started looking at the SNVS System Security Monitor. If you have some other avenue that we can look at, please let us know.

Some other things of note:

 - this only happens if the wdog reset we are using, also issues the WDOG_B signal.

 - we are not having this problem when we are running on battery, without AC connection.

 - on the problematic boards, this only starts happening a couple of minutes after the initial COLD POWER ON. This means that the first couple of resets will not manifest the SNVS_LP register reset, while any subsequent reset will always manifest it.

 

Thanks in advance.

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weidong_sun
NXP TechSupport
NXP TechSupport

Hello Alexandru,

>>we are not having this problem when we are running on battery, without AC connection.

(1)The battery you mentioned is the working battery of the board, not the li coin cell battery of snvs, right?

(2)If yes, the batter is used to supply PIMC, right?

>>on the problematic boards, this only starts happening a couple of minutes after the initial COLD POWER ON. This means that the first couple of resets will not manifest the SNVS_LP register reset, while any subsequent reset will always manifest it.

If VSNVS_3V0 is stable, no any drops during COLD RESET, SNVS_LP shouldn't be changed.

In addition, would you like to attach your schematic here?

Have a nice day!

BR,

weidong

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weidong_sun
NXP TechSupport
NXP TechSupport

Hello Alexandru,

  See my advice below, please!

1. In order to keep the contents of snvs register or RTC unchanged, it is necessary to ensure that vsnvs_3v0 power supply is stable.

See schematic below, please!

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pastedImage_2.png

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2. If your reset is operating PWRON pin of PMIC, it means cold reset occurs, which  is equivalent to powering the board off and then back on,so at the moment of power off, P3V15_LICELL must supply power to VDD snvs in. This is to ensure that the contents of snvs register are not lost.

3. for your questions

You have some boards that are normal and some boards that are abnormal. Therefore, it is recommended that you first check whether the power of Li coin cell is normal, without doubting the snvs module inside the CPU.

Hope above advice is helpful for you!

Have a nice day!

BR,

Weidong

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