Reset Core 1, 2 and 3 in iMX6

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Reset Core 1, 2 and 3 in iMX6

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tiagoduarte
Contributor II

Dear all,

I'm working in a project for the University and the main goal was accomplished. The goal was to port a RTOS in bare-metal to the Nitrogen6x board, based in the iMX6 chip.

Core 0 is running the OS and my next goal was to perform tasks with the other cores (1, 2 and 3).

With this in mind I configured the SRC registers in this order (just for Core 1, for now):

     1 - Wrote the address of the function that I wanted in the register that holds entry function for CPU1 - SRC_GPR3 (The function was just a print in a while loop to verify that it was working.)

     2 - Enable the Core 1 by setting the bit 22 in the SRC_SCR.

Nothing happened.

After I reconfigured the startup code of the OS to support multiple cores. And my idea was to differentiate the primary core (Core 0) from the secondary cores (Core 1, 2 and 3) and jump to different functions, the primary core will jump to the main of the OS and the secondary cores will jump to my printf in a while function.

I re-configured the SRC registers in this order:

     1 - Wrote the address of the startup function in the register that holds entry function for CPU1 - SRC_GPR3.

     2 - Wrote the address of the function (the printf in a while loop) in the register that holds argument of entry function for CPU1 - SRC_GPR4. the startup code was jumping to this address after the initializations.

     3 - Enable the Core 1 by setting the bit 22 in the SRC_SCR.

Non of this methods worked and I could put the secondary cores working.

I have a JTAG connection to the Core 0 using openocd but unfortunately I can't connect it to the other cores because of the lack of support in the openocd documentation. I can only load and debug the Core 0 and I don't know in which state U-Boot puts the secondary cores in the cluster.

I would like to know what I'm doing wrong or if there is another process to initiate the secondary cores in a iMX6 chip.

Thanks in advance,

Tiago Duarte

University of Minho

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AnsonHuang
NXP Employee
NXP Employee

Hi, Tiago

     I think the problem of your flow is you didn't do reset as well as enabling secondary core. As long as you write the entry function physical address into the SRC_GPR3 and doing a reset along with enable, they are both in SRC_SCR register, every core has a enable bit and reset bit. Then CORE1 will do reset,  jump to ROM code, and in ROM code, it checks whether the entry address is valid, if yes, it will jump to the entry address.

     See below our flow of booting up a secondary core, if it still not work, then I suspect there is something wrong with your entry function address, it must be physical address and accessable.

75         /* set entry point for cpu1-cpu3*/

76         boot_entry = virt_to_phys(mx6_secondary_startup);

77

78         writel(boot_entry, src_base + SRC_GPR1_OFFSET + 4 * 2 * cpu);

79         writel(0, src_base + SRC_GPR1_OFFSET + 4 * 2 * cpu + 4);

80

84

85         /* reset cpu<n> */

86         val = readl(src_base + SRC_SCR_OFFSET);

87         val |= 1 << (BP_SRC_SCR_CORE0_RST + cpu);   /* Do enable and reset together */

88         val |= 1 << (BP_SRC_SCR_CORES_DBG_RST + cpu);

89         writel(val, src_base + SRC_SCR_OFFSET);

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tiagoduarte
Contributor II

Hi, Yongcai.

Thanks for the fast reply. It solved my problem.

I was doing the reset of all cores in the beginning of main and I set the registers with the entry function and doing the enabling of cores after.

Cheers,

Tiago Duarte

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AnsonHuang
NXP Employee
NXP Employee

Hi, Tiago

Great, can you set the question as resolved if you didn’t have other questions, thanks in advanced!

Best Regards.

Anson huang 黄勇才

Freescale Semiconductor Shanghai

上海浦东新区亮景路192号A座2楼

201203

Tel:021-28937058

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AnsonHuang
NXP Employee
NXP Employee

Hi, Tiago

     I think the problem of your flow is you didn't do reset as well as enabling secondary core. As long as you write the entry function physical address into the SRC_GPR3 and doing a reset along with enable, they are both in SRC_SCR register, every core has a enable bit and reset bit. Then CORE1 will do reset,  jump to ROM code, and in ROM code, it checks whether the entry address is valid, if yes, it will jump to the entry address.

     See below our flow of booting up a secondary core, if it still not work, then I suspect there is something wrong with your entry function address, it must be physical address and accessable.

75         /* set entry point for cpu1-cpu3*/

76         boot_entry = virt_to_phys(mx6_secondary_startup);

77

78         writel(boot_entry, src_base + SRC_GPR1_OFFSET + 4 * 2 * cpu);

79         writel(0, src_base + SRC_GPR1_OFFSET + 4 * 2 * cpu + 4);

80

84

85         /* reset cpu<n> */

86         val = readl(src_base + SRC_SCR_OFFSET);

87         val |= 1 << (BP_SRC_SCR_CORE0_RST + cpu);   /* Do enable and reset together */

88         val |= 1 << (BP_SRC_SCR_CORES_DBG_RST + cpu);

89         writel(val, src_base + SRC_SCR_OFFSET);

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